C.D. Chalk

Applying a robust heteroscedastic probabilistic neural network to analog fault detection and classification

The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques such as neural networks have been employed to automate classification. The major drawback to such techniques has been the implicit assumption that the variances of the responses of faulty circuits have been the same as each other and the same as that of the fault-free circuit. This assumption can be shown to be false. Neural networks, moreover, have proved to be slow. This paper describes a new neural network structure that clusters responses assuming different means and variances. Sophisticated statistical techniques are employed to handle situations where the variance tends to zero, such as happens with a fault that causes a response to be stuck at a supply rail. Two example circuits are used to show that this technique is significantly more accurate than other classification methods. A set of responses can be classified in the order of 1 s.

Generation and verification of tests for analogue circuits subject to process parameter deviations

The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analogue multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold, although they appear lower.

Fault Modeling and Simulation Using VHDL-AMS

Fault simulation is an accepted part of the test generation procedure for digital circuits. With complex analog and mixed-signal integrated circuits, such techniques must now be extended. Analog simulation is slow and fault simulation can be prohibitively expensive because of the large number of potential faults. We describe how the number of faults to be simulated in an analog circuit can be reduced by fault collapsing, and how the simulation time can be reduced by behavioral modeling of fault-free and faulty circuit blocks. These behavioral models can be implemented in SPICE or in VHDL-AMS and we discuss the merits of each approach. VHDL-AMS does potentially offer advantages in tackling this problem, but there are a number of computational difficulties to be overcome.

Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations

The paper presents a test stimulus generation and fault simulation methodology for the detection of catastrophic faults in analog circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analog multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold.

Analogue fault modelling and simulation for supply current monitoring

Fault simulation of analogue circuits is a very CPU intensive task. This paper describes a technique to increase the speed of fault simulation. The effects of bridging faults within operational amplifiers have been classified according to the externally observable behaviour reducing the number of fault simulations by two thirds. Parameterisable macromodels have been written in which both fault-free specifications and faulty effects can be modelled. The supply current is also modelled. These macromodels have been verified by embedding within a larger circuit, and have been shown to accurately model fault-free and faulty behaviour, and to propagate faulty effects correctly. The macromodels simulate about 7.5 times faster than the full transistor model.

A design for test technique to increase the resolution of analogue supply current tests

By employing the new DFT technique proposed here, the fault coverage of the AC RMS supply current test for an opamp within a CMOS analogue multiplier circuit was increased to 100%. The DFTT scheme is based on reducing the width of high current transistors during the test.