C. Furbock

Quantitative internal thermal energy mapping of semiconductor devices under short current stress using backside laser interferometry

In the backside interferometric thermal mapping technique, an infrared (IR) laser beam probes the temperature-induced changes in the semiconductor refractive index inside a semiconductor device, which results in a change in the measured optical phase shift. In this paper, a theoretical analysis of the phase shift is reported. The focus is on nanosecond-to-microsecond time-scale thermal mapping during high current stress, as occurring e.g., during an electrostatic discharge (ESD) event or in some power applications. An analytical expression for phase shift is obtained from the analysis of the thermal diffusion equation. The phase shift is directly proportional to the two-dimensional (2-D) heat energy density in the semiconductor active region of the device. The phase shift is also expressed in terms of the local dissipated heat energy and the heat transferred to the device top and lateral sides. In addition, the space integral of the phase shift is expressed in terms of a total energy dissipated in the device and the total heat transferred from the semiconductor to the top device layers. The theory shows an excellent agreement with experimental data obtained for a p-n diode ESD protection structure working in the avalanche regime.

Scanning heterodyne interferometer setup for the time-resolved thermal and free-carrier mapping in semiconductor devices

An automated scanning interferometer setup for time resolved measurement of thermal and free carrier distribution in semiconductor devices during short stress pulses is presented. The semiconductor device is probed via the thermal and free carrier induced changes in the semiconductor refractive index using a heterodyne interferometer. The setup integrates device stressing facilities, data acquisition and laser beam scanning. The time and space resolutions are 3 ns and 1.5 /spl mu/m, respectively. Different modes of interferometer configurations are discussed with respect to their application. A program for the extraction of the optical phase shift and calculation of the power dissipation density from the optical signal is also presented. The error due to measurement accuracy, as well as that introduced by the data post processing, is estimated.

Single-shot thermal energy mapping of semiconductor devices with the nanosecond resolution using holographic interferometry

A novel two-dimensional backside optical imaging method for thermal energy mapping inside semiconductor devices is presented. The method is based on holographic interferometry from the device backside and uses the thermo-optical effect. An image of the local thermal energy is obtained with 5-ns time resolution using a single stress pulse. The technique allows a unique recording of the internal device behavior. The method is demonstrated analyzing the nonrepetitive thermal and current flow dynamics in smart power electrostatic discharge (ESD) protection devices. A spreading of the current during the stress pulse is observed and explained by the effect of the negative temperature dependence of the impact ionization coefficient.

Thermal and free carrier concentration mapping during ESD event in smart Power ESD protection devices using an improved laser interferometric technique

Abstract Spatial distribution of temperature and free-carrier concentration during high-current stress is studied in smart power electrostatic discharge (ESD) protection devices using a backside laser interferometric technique. The method is based on detecting changes in the refractive index of silicon due to thermo-optical and plasma-optical effects. We use a modified version of a heterodyne interferometer, where the reference beam is reflected from an external mirror outside the sample chip, which allows one to perform measurements without any restriction to the size of the scanning area. We have found two pronounced heat dissipating regions due to a vertical and a lateral current flow path in the device. In addition, two regions with increased current density due to carrier injection related to the two current paths have been found. These temperature and carrier concentration distributions found by the experiment agree very well with the results of 2D device simulation.

Simulation and experimental study of temperature distribution during ESD stress in smart-power technology ESD protection structures

Electro-thermal simulation and a laser-interferometric thermal mapping technique are employed to study temperature distribution and dynamics in smart power technology electrostatic discharge (ESD) protection npn transistor devices during a high current stress. The simulation predicts two temperature peaks along the device length which are due to a vertical and lateral current pathway in the studied devices. The temperature distribution in the device is studied via the measurements of the temperature-induced optical phase shift from the device backside. The position of the temperature peaks, their temporal evolution and stress level dependence obtained by experiment and simulation are in good agreement.

Study of triggering inhomogeneities in gg-nMOS ESD protection devices via thermal mapping using backside laser interferometry

Abstract Inhomogeneities in the parasitic bipolar transistor triggering during an electrostatic discharge (ESD) event are analyzed in 0.35 μm technology grounded-gate nMOSFET ESD protection devices operating in snapback. The current density during high current stress is studied by monitoring the temperature-induced increase in optical phase shift using a backside infrared laser interferometric technique. The distribution of the current along the gate width and the triggered width are investigated as a function of the applied stress current magnitude and device layout parameters. Below a critical stress current the parasitic bipolar transistor triggers inhomogeneously, first at the corners and then in the central part of the device. Under these conditions the current density in the triggered region of the device is nearly constant. At stresses higher than the critical current the device is homogeneously triggered, exhibiting a linear increase of the current density with the stress current in the device. The experimental results are explained in terms of 3D layout effects and compared to results of 3D electrical device simulation.

Bulk and surface degradation mode in 0.35μm technology gg-nMOS ESD protection devices

Abstract We study failure mechanisms in 0.35μm process grounded-gate nMOS electrostatic discharge (ESD) protection devices stressed by high current - ESD like - pulses. Stress evolution of leakage current and low frequency noise is correlated with the position of the ESD damage analyzed using optical beam induced current (OB1C) technique. While a kink-free-like IV characteristics and low noise magnitude are typical for a bulk damage at the drain-contact region, a kink-like IV shape and large random telegraph signal (RTS) noise accompanies surface damage under the gate oxide. The role of hot-carriers in the degradation of the Si Si0 2 interface and gate oxide, and leakage current mechanism are discussed.

Single-shot nanosecond thermal imaging of semiconductor devices using absorption measurements

A nonscanning optical method for single-shot thermal imaging of semiconductor devices is presented. The method detects changes in the band-to-band absorption due to local self-heating effects. The device is illuminated from the substrate side and the image reflected from the device topside is detected. The illumination wavelength is set near the semiconductor absorption edge. The time resolution is 5 ns, determined by the laser pulsewidth and the space resolution is about 2 /spl mu/m. The method is applied to study the transient current distribution in electrostatic discharge (ESD) protection devices fabricated in smart power technology. The observed current spreading with time is explained in terms of a negative temperature dependence of the impact ionization coefficient. The method allows a fast analysis of the current-flow homogeneity in ESD protection and power devices.

Laser interferometric mapping of smart power ESD protection devices with different blocking capabilities

We study thermal and free carrier distribution during electrostatic discharge (ESD) stress in npnp and anti-serial npn transistor ESD protection devices with different blocking capability. The thermal energy and free carrier distribution is studied using the measurements of temperatureand free carrier-induced optical phase shift. The dominant heat source in the npnp (anti-serial npn) device is due to a lateral (vertical) current flow. This is due to a different layout of the devices which also explains their different ruggedness.

Investigation of 3D Phenomena in the Triggering of gg-nMOS Electrostatic Discharge Protection Devices

We study inhomogeneity in the triggering of the parasitic bipolar transistor during high current stress in the 0.35 μm process grounded-gate nMOS electrostatic discharge (ESD) protection devices by a laser interferometric technique. The current density and triggering width in partially and fully triggered devices are studied as a function of stress current. On the basis of experiments, 3D simulation and a simple model we explain the observed high current I-V characteristics.