Sergey Bychikhin

Transient thermal characterization of AlGaN/GaN HEMTs grown on silicon

We studied a temperature increase and a heat transfer into a substrate in a pulsed operation of 0.5 length and 150 /spl mu/m gate width AlGaN/GaN HEMTs grown on silicon. A new transient electrical characterization method is described. In combination with an optical transient interferometric mapping technique and two-dimensional thermal modeling, these methods determine the device thermal resistance to be /spl sim/70 K/W after 400 ns from the start of a pulse. We also localized the high-electron mobility transistor heat source experimentally and we extracted a thermal boundary resistance at the silicon-nitride interface of about /spl sim/7/spl times/10/sup -8/ m/sup 2/K/W. Thermal coupling at this interface may substantially influence the device thermal resistance.

Quantitative internal thermal energy mapping of semiconductor devices under short current stress using backside laser interferometry

In the backside interferometric thermal mapping technique, an infrared (IR) laser beam probes the temperature-induced changes in the semiconductor refractive index inside a semiconductor device, which results in a change in the measured optical phase shift. In this paper, a theoretical analysis of the phase shift is reported. The focus is on nanosecond-to-microsecond time-scale thermal mapping during high current stress, as occurring e.g., during an electrostatic discharge (ESD) event or in some power applications. An analytical expression for phase shift is obtained from the analysis of the thermal diffusion equation. The phase shift is directly proportional to the two-dimensional (2-D) heat energy density in the semiconductor active region of the device. The phase shift is also expressed in terms of the local dissipated heat energy and the heat transferred to the device top and lateral sides. In addition, the space integral of the phase shift is expressed in terms of a total energy dissipated in the device and the total heat transferred from the semiconductor to the top device layers. The theory shows an excellent agreement with experimental data obtained for a p-n diode ESD protection structure working in the avalanche regime.

Low-frequency noise sources in as-prepared and aged GaN-based light-emitting diodes

The low-frequency noise sources are investigated in as-prepared and aged GaN light-emitting diodes (LEDs). Accelerated aging is performed by thermal (300h at 240°C) and electrical forward-bias stressing (20 and 50mA for 2500h). At low currents I<IRTS, where IRTS is a critical current, the low-frequency noise is dominated by random telegraph signal (RTS) noise on top of the 1∕f noise. An explanation is given for the giant relative current jumps ΔI∕I≈50% and an expression for IRTS is derived. The RTS noise in our devices is a less-sensitive diagnostic tool for studying the results of accelerated aging. Two components of the 1∕f noise were observed: one is related to the quantum-well junction and the other is due to series resistance noise. The two 1∕f spectra have different current dependences. It was found that the junction 1∕f noise is not significantly affected by aging. However, a strong increase in series resistance noise, by a factor of 60–800 compared to unstressed devices, is observed after strong e...

Investigation of the thermal boundary resistance at the III-Nitride/substrate interface using optical methods

Heat removal from III-Nitride-based devices into a substrate depends also on an acoustic coupling at III-Nitride/substrate interface. We investigate thermal boundary resistance (TBR) and its effects on temperature distribution for GaN layers on Si, SiC, or sapphire substrates. Micro-Raman method is used for the investigation of TBR at the GaN/Si interface while the transient interferometric mapping (TIM) method is used for investigation of GaN/SiC and GaN/sapphire systems. Thermal modeling is used to analyze the experimental data. We found TBR to be ∼7×10−8 m2 K/W for GaN/Si and ∼1.2×10−7 m2 K/W for GaN/SiC interfaces. The role of TBR at the GaN/sapphire interface in the poor heat transfer from GaN to substrate is found to be less important. It is suggested that the substrate cooling efficiency may be improved if fewer defects are present at the interface to the GaN epistructure.

Scanning heterodyne interferometer setup for the time-resolved thermal and free-carrier mapping in semiconductor devices

An automated scanning interferometer setup for time resolved measurement of thermal and free carrier distribution in semiconductor devices during short stress pulses is presented. The semiconductor device is probed via the thermal and free carrier induced changes in the semiconductor refractive index using a heterodyne interferometer. The setup integrates device stressing facilities, data acquisition and laser beam scanning. The time and space resolutions are 3 ns and 1.5 /spl mu/m, respectively. Different modes of interferometer configurations are discussed with respect to their application. A program for the extraction of the optical phase shift and calculation of the power dissipation density from the optical signal is also presented. The error due to measurement accuracy, as well as that introduced by the data post processing, is estimated.

Single-shot thermal energy mapping of semiconductor devices with the nanosecond resolution using holographic interferometry

A novel two-dimensional backside optical imaging method for thermal energy mapping inside semiconductor devices is presented. The method is based on holographic interferometry from the device backside and uses the thermo-optical effect. An image of the local thermal energy is obtained with 5-ns time resolution using a single stress pulse. The technique allows a unique recording of the internal device behavior. The method is demonstrated analyzing the nonrepetitive thermal and current flow dynamics in smart power electrostatic discharge (ESD) protection devices. A spreading of the current during the stress pulse is observed and explained by the effect of the negative temperature dependence of the impact ionization coefficient.

Extraction of spatio-temporal distribution of power dissipation in semiconductor devices using nanosecond interferometric mapping technique

A method for the extraction of power dissipation sources inside semiconductor devices on a nanosecond-time scale is proposed using a backside transient interferometric mapping technique. The two-dimensional power dissipation density is extracted from the time and space derivative of the measured optical phase shift. The method is applied to the analysis of moving current filaments in an electrostatic discharge protection device operating in the avalanche regime. It is found that the filament dynamics is governed by the negative temperature dependence of the impact ionization coefficient. The total power calculated from the optical measurements is in excellent agreement with the electrical input power.

Accurate Temperature Measurements of DMOS Power Transistors up to Thermal Runaway by Small Embedded Sensors

Intrinsic device temperature is one of the most important limits of the safe operating area and of the reliability of power double-diffused metal-oxide-semiconductor (DMOS) transistors. Therefore, precise knowledge of the temperatures throughout the device, up to the onset of thermal runaway is required. However, standard methods that measure the surface temperature, such as infrared thermography, usually cannot be applied to most advanced power technologies. Therefore, we propose to embed very small temperature sensors within the active DMOS cell array itself. These sensors are located very close to the heat-generating regions, having a tight thermal coupling, thus giving an accurate measurement of the intrinsic device temperature. Moreover, due to their small size, many sensors can be integrated into a power DMOS for a good spatial resolution. The sensors have been implemented in a smart power production technology. Calibration and verification up to 600 °C, as well as further validation up to 400 °C, by comparison to transient interferometric mapping measurements are discussed. The usefulness of the sensors is demonstrated by characterization of the thermal runaway, by measurements with a high spatial resolution achieved by 60 sensors in conjunction with an on-chip multiplexer, and by an assessment of the peak temperature reduction that can be obtained by using thick power metal layers for increased heat capacitance.

Small embedded sensors for accurate temperature measurements in DMOS power transistors

Device temperature is one of the most important limits for the safe operating area and the reliability of power DMOS transistors. Therefore, accurate measurements of their intrinsic device temperature are required. However, standard methods such as IR thermography usually cannot be applied to advanced smart power technologies where a thick power metal layer obscures the - often significantly hotter - active device area. Thus, we propose to embed very small temperature sensors in the active DMOS cell array. These sensors allow for an accurate reading of the intrinsic device temperature while not influencing the DMOS behavior noticeably. The sensors are calibrated up to 600°C, validated by comparison to TIM measurements up to 400°C, and used to investigate thermal runaway. Results from 60 sensors embedded in one large power DMOS with on-chip analog multiplexing are also presented.

Transient behavior of SCRS during ESD pulses

Silicon controlled rectifiers (SCRs) are widely used ESD protection elements exhibiting extremely good voltage clamping and high failure current threshold. However, the turn-on behavior of the SCR is often a matter of concern. A detailed transient study of the 3-D current and temperature distribution in a SCR during a high current square pulse is presented leading to design options with shorter delay between trigger point and full clamp performance.