Viktor Dubec

Moving current filaments in integrated DMOS transistors under short-duration current stress

Integrated vertical DMOS transistors of a 90-V smart power technology are studied under short-duration current pulses. Movement of current filaments and multiple hot spots observed by transient interferometric mapping under nondestructive snap-back conditions are reported. Device simulations show that the base push-out region associated with the filament can move from cell to cell along the drain buried layer due to the decrease of the avalanche generation rates by increasing temperature. The influence of the termination layout of the source field on the hot-spot dynamics is studied. Conditions for filament motion are discussed. The described mechanisms help homogenizing the time averaged current-density distribution and enhance the device robustness against electrostatic discharges.

Single-shot thermal energy mapping of semiconductor devices with the nanosecond resolution using holographic interferometry

A novel two-dimensional backside optical imaging method for thermal energy mapping inside semiconductor devices is presented. The method is based on holographic interferometry from the device backside and uses the thermo-optical effect. An image of the local thermal energy is obtained with 5-ns time resolution using a single stress pulse. The technique allows a unique recording of the internal device behavior. The method is demonstrated analyzing the nonrepetitive thermal and current flow dynamics in smart power electrostatic discharge (ESD) protection devices. A spreading of the current during the stress pulse is observed and explained by the effect of the negative temperature dependence of the impact ionization coefficient.

Thermal distribution during destructive pulses in ESD protection devices using a single-shot two-dimensional interferometric method

Thermal distribution during single destructive electrostatic discharge (ESD) events is investigated in smart power ESD protection devices using a two-dimensional holographic interferometry technique. The hot spot dynamics and the position of destructive current filaments is correlated with the thermal distribution under the nondestructive conditions and with the failure analysis results.

Thermal imaging of smart power DMOS transistors in the thermally unstable regime using a compact transient interferometric mapping system

Smart power DMOSes are analyzed under thermally unstable conditions up to the destruction level using a new compact version of the transient interferometric mapping (TIM) method. High accuracy phase measurements are achieved employing superluminescent diodes and focal plane array cameras. Two-dimensional thermal mapping at two time instants during a single stress pulse is performed in the range of 100 μs to few milliseconds. The size of the region where the parasitic bipolar transistor becomes thermally activated at the onset of thermal runaway is determined. The results are correlated to conventional failure analysis.

Error analysis in phase extraction in a 2D holographic imaging of semiconductor devices

Backside transient interferometric mapping method is a useful tool for ns-resolution imaging of transient changes in heat energy and free carrier concentration in semiconductor devices during high-energy electrical pulses. In this contribution we investigate the sources of errors in the extracted phase, which are specific to the spatial phase and reflectivity profile of the semiconductor device structure and to the used FFT extraction method. We show that the phase and reflectivity profile of the sample related to the structure of the top layers causes undulations in the phase, thus decreasing the phase extraction precision. To minimize the undulations, an optimal spectrum filter for the FFT method is proposed. In addition, the noise and fringe discontinuities are found to result in defects in the phase profile. In order to isolate these defects time efficiently, a pre-processing of the wrapped phase image is proposed. It effectively reduces the requirement for the unwrapping to a small region. The path independent method or the pixel-queue algorithm is then used for the unwrapping, which do not allow spreading of the defects. The findings are used to make a full-automated evaluation of the phase images.

Interaction of traveling current filaments and its relation to a nontrivial thermal breakdown scenario in avalanching bipolar transistor

Traveling multiple current filaments (CFs) are investigated by transient interferometric mapping method in avalanching bipolar n-p-n transistors. The number of CFs can vary for identical current pulses and their averaged number increases with the total current. The CF movement is driven by a temperature gradient in it, caused by the self-heating effect. For pulses of 500 ns duration, the existence of two CFs appears dangerous as it causes a nontrivial premature thermal breakdown (TB), which does not occur when only one CF exists at the same current level. TB occurs due to redistribution of current between the two CFs. The current components flowing through each CF depend on CF temperature and are globally coupled by a fixed device current. When a first CF reaches the device end, it heats up and disappears due to vanishing impact ionization rate in it. When a second traveling CF, taking consequently the whole current, reaches the already preheated device end, a TB event occurs. The transition from two to o...

Analysis of triggering behaviour of high voltage CMOS LDMOS clamps and SCRs during ESD induced latch-up

Current flow uniformity during ESD induced latch-up event is investigated in multi-finger LDMOS clamps and SCR ESD protection devices fabricated in a 0.6 μm high voltage CMOS process. Current flow, excess free carrier and hot spot distribution are analyzed by transient interferometric mapping technique combined with a latch-up pulse system consisting of a solid state pulser and a clear pulse unit. During latch-up, the current in the LDMOS clamps flows just in a single spot and the failure position is random and independent on device type. The position of the failure site correlates with the trigger position of the device. The SCRs exhibit pulse-to-pulse instabilities in the current flow.

Single-shot nanosecond thermal imaging of semiconductor devices using absorption measurements

A nonscanning optical method for single-shot thermal imaging of semiconductor devices is presented. The method detects changes in the band-to-band absorption due to local self-heating effects. The device is illuminated from the substrate side and the image reflected from the device topside is detected. The illumination wavelength is set near the semiconductor absorption edge. The time resolution is 5 ns, determined by the laser pulsewidth and the space resolution is about 2 /spl mu/m. The method is applied to study the transient current distribution in electrostatic discharge (ESD) protection devices fabricated in smart power technology. The observed current spreading with time is explained in terms of a negative temperature dependence of the impact ionization coefficient. The method allows a fast analysis of the current-flow homogeneity in ESD protection and power devices.

Thermal distribution during destructive pulses in ESD protection devices using a single-shot, two-dimensional interferometric method

Thermal distribution during single destructive electrostatic discharge (ESD) events is investigated in smart power ESD protection devices using a novel two-dimensional holographic interferometry technique. The hot spot dynamics and position of destructive current filaments is correlated with the thermal distribution under the non-destructive conditions and with the failure analysis results.

Automated setup for thermal imaging and electrical degradation study of power DMOS devices

An automated setup for investigation of degradation mechanisms in semiconductor devices under electrostatic discharge (ESD) stress is presented. Vertical-DMOS transistors of a Smart Power technology operating in bipolar snapback mode are studied by combined techniques. The current filamentary behavior imaged by a two-instants transient interferometric mapping (TIM) method and the variation of device DC characteristics are studied as a function of stress current. During repeated stress, a progressive degradation of the DC leakage current at the failure level and a slight gradual change of transfer characteristics are observed. The failure location, resolved in three dimensions by backside infrared microscopy, agrees with the position obtained from the TIM analysis and expected from device physics.