C. L. Liu

A New Algorithm for Floorplan Design

We present in this paper a new algorithm for floorplan design using the method of simulated annealing. The major contributions of the paper are: 1. A new representation of floorplans (normalized Polish expressions) which enables us to carry out the neighborhood search effectively. 2. A simultaneous minimization of area and total interconnection length in the final solution. Experimental results indicate that the algorithm performs well in many test problems.

Minimum crosstalk channel routing

As technology advances, interconnection wires are placed in closer proximity and circuits operate at higher frequencies. Consequently, reduction of crosstalk between interconnection wires becomes an important consideration in VLSI design. In this paper, we study the gridded channel routing problem with the objective of satisfying crosstalk constraints for the nets. We proposed a new approach to the problem which utilizes existing channel routing algorithms and improves upon the routing results by permuting the routing tracks. The permutation problem is proven to be NP-complete. A novel mixed ILP formulation and effective procedures for reducing the number of variables and constraints in the mixed ILP formulation are then presented. The new algorithm is tested on three large benchmark circuits as well as many randomly generated circuits. The experimental results are very promising.

Minimum fault coverage in reconfigurable arrays

The authors discuss the case in which the redundant elements are arranged in the form of spare rows and spare columns for a rectangular array. Redundant RAMs are examples of such case. A covering is set of rows and columns that are to be replaced by spare rows and spare columns so that all defective elements are replaced. The authors introduce the notion of a critical set, which is a maximum set of rows and columns that must be included in any minimum covering. They show that for a given pattern of defective elements the corresponding critical set is unique. They also present a polynomial-time algorithm for finding the critical set and demonstrate how the concept of critical sets can be used to solve a number of fault-coverage problems.<<ETX>>

Floorplan design of VLSI circuits

In this paper we present two algorithms for the floorplan design problem. The algorithms are quite similar in spirit. They both use Polish expressions to represent floorplans and employ the search method of simulated annealing. The first algorithm is for the case where all modules are rectangular, and the second one is for the case where the modules are either rectangular or L-shaped. Our algorithms consider simultaneously the interconnection information as well as the area and shape information for the modules. Experimental results indicate that our algorithms perform well for many test problems.

General models and algorithms for over-the-cell routing in standard cell design

When an over-the-cell routing layer is available for standard cell layout, efficient utilization of routing space over the cells can significantly reduce layout area. In this paper, we present three physical models to utilize the area over the cells for routing in standard cell designs. We also present efficient algorithms to choose and to route a planar subset of nets over the cells so that the resulting channel density is reduced as much as possible. For each of the physical models, we show how to arrange inter-cell routing, over-the-cell routing and power/ground busses to achieve valid routing solutions. Each algorithm exploits the particular arrangement in the corresponding physical model and produces provably good results in polynomial time. We tested our algorithms on several industrial standard cell designs. In our tests, this method reduces total channel density as much as 21%.

A new performance driven placement algorithm

The authors present a novel performance driven placement algorithm. They use a convex programming algorithm to compute a set of upper bounds on the net wire lengths. A modified min-cut algorithm is then used to generate a placement with the objective of minimizing the number of nets, the wire lengths of which exceed their corresponding upper bounds. The situation in which the modified min-cut algorithm fails to generate a placement that satisfies the timing requirements is addressed, and an iterative approach is used to modify the set of upper bounds making use of information from previous placements. The algorithm was implemented in C and tested on eight problems on a Sparc 2 workstation.<<ETX>>

A performance driven macro-cell placement algorithm

The authors present a new performance driven macro-cell placement algorithm. Placement of modules is guided by a set of upper- and lower-bounds on the net wire lengths. A convex programming algorithm is used to compute a set of upper-bounds on the net wire lengths which will ensure that timing requirements between input and output signals are satisfied. A set of lower-bounds is also computed to control signal skews at intermediate points of the circuit. Artificial nets are introduced between all pairs of modules. Lower-bounds on the lengths of the artificial nets are computed to avoid module overlaps in the placement. A modified min-cut placement algorithm is then used to generate a placement that satisfies the upper- and lower-bounds. An iterative procedure is used to modify the set of upper- and lower-bounds to improve the quality of the placement result. Experimental results on eight test examples are included.<<ETX>>

A new approach to three- or four-layer channel routing

An approach to the three-layer or four-layer channel-routing problem is presented. A general technique that transforms a two-layer routing solution systematically into a three-layer routing solution is developed. The proposed router performs well in comparison with other three-layer channel routers proposed thus far. In particular, it provides a ten-track optimal solution for the famous Deutschs difficult example, whereas other well-known three-layer channel routers required 11 or more tracks. The approach is extended to four-layer channel routing. Given any two-layer channel-routing solution without an unrestricted dogleg that uses w tracks, the router can obtain a four-layer routing solution using no more than w/2 tracks. A theoretical upper bound d/2+2 for arbitrary four-layer channel routing problems is also given. >

Area minimization for floorplans

In this paper we study the area minimization problem in floorplanning (also known as the floorplan sizing problem). For a given floorplan, the problem is to select a layout alternative for each subcircuit on a chip so as to minimize the chip area. Two area minimization methods for general floorplans are proposed. Both methods can be viewed as generalizations of the classical algorithm for slicing floorplans of Otten (1982) and Stockmeyer (1983) in the sense that they reduce naturally to their algorithm for slicing floorplans. Compared with the branch-and-bound algorithm of Wimer et al (1989), which does not have a nontrivial performance bound, our methods are provably better than an exhaustive method for all the examples we examined. >

Utilization of Multiport Memories in Data Path Synthesis

In this paper, a new approach to the problem of allocating multiport memory modules for data storage is presented. Previous approaches divide the allocation problem into two separate steps: (i) grouping the variables (or registers) to form memory modules and (ii) determining the interconnections between the memory modules and functional units. Yet, there is no easy way to predict the result of step (ii) during step (i). In our approach, we place primary importance on the cost of interconnections. Consequently, we try to minimize the cost of interconnections first and then to group the variables to form memory modules later. For a number of benchmark problems, it has been shown that this approach is quite effective.