C. Le Royer

Impact of SOI, Si 1-x Ge x OI and GeOI substrates on CMOS compatible Tunnel FET performance

We report for the first time experimental investigations on SOI, Si1-xGexOI & GeOI Tunnel FET (TFET). These devices were fabricated using a Fully Depleted SOI CMOS process flow with high k-metal gate stack, enabling 2 decades lower IOFF (~30fA/mum) compared to co-processed CMOS. We successfully solve the TFET bipolar parasitic conduction by a novel TFET architecture, the Drift Tunnel FET (DTFET), with improved OFF state control. Concerning the ON current issue, we improve the SOI p (resp. n) TFET ION by a factor 55 (resp. 8) by source-drain profiles optimization (via spacers & extensions). Moreover, we demonstrate for the first time functional TFET & CMOS devices on Si1-xGexOI (x=15-30-100%) co-integrated with the same SOI process flow, enabling TFET ION continuous improvement with Ge content increase: ION x2700 for GeOI (compared to SOI).

Advances, challenges and opportunities in 3D CMOS sequential integration

3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices. Finally, the development of a stable salicide enables to retain bottom performance after top FET processing. Overcoming these major technological issues offers a wide range of applications.

Advances in 3D CMOS sequential integration

For the first time 3D sequential CMOS integration turns up to be an actual competitor for sub 22nm technology nodes. Thanks to the original use of molecular bonding, high quality top Si active layers are obtained. Thermally robust bottom salicide goes through the whole top FET processing without any significant sheet resistance degradation. The low temperature integration of raised source and drain for top layers is demonstrated. A decrease by 4Å of the Equivalent Oxide Thickness is measured when a low thermal budget process is implemented. The electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm. It leads to a threshold voltage dynamic shift of 130mV enabling SRAM stabilization.

Engineered substrates for future More Moore and More than Moore integrated devices

In 1991, M. Bruel (1) invented and patented the Smart Cut technology to fabricate Silicon On Insulator (SOI) substrates. The process relies on the transfer of a high quality single crystal layer from one wafer to another: implantation of gaseous ions in a single crystal wafer, direct bonding on a stiffener and splitting (Fig 1). The invention of this SOI process combined with the entrepreneurship of SOITEC paved the way to high quality SOI substrates mass production. Today, SOI is a mature product (up to 300mm diameter) and now developments are focused on the integration of new materials and functionalities in order to improve device performances and enlarge the application spectrum.

Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS

Epitaxial strained Si and Ge n- and p-MOSFETs with a TiN/HfO2 gate stack were fabricated with the same process for a dual channel integration scheme. Compared to the HfO2/Si reference, X1.7 strained Si electron and X9 strained Ge hole mobility gains are demonstrated, achieving symmetric n- and p-MOSFET IDsat performance. This X9 strained Ge hole mobility enhancement highly exceeds previous reported results on Ge pMOSFETs with high-k dielectrics. For the first time, such a hole mobility enhancement, theoretically predicted and experimentally reported with thick SiO2 gate dielectrics, is demonstrated with a thin high-k gate dielectric (EOT=14Aring)

Localized ultra-thin GeOI: An innovative approach to germanium channel MOSFETs on bulk Si substrates

In this paper we compare two innovative approaches to the integration of Ge-channel on Insulator MOSFETs from conventional Bulk-Si substrates. The first one is based on the Ge-condensation process, and the second one relies on the epitaxy of a pure ultra-thin 2.3 nm-thick Ge layer performed directly on Si. With the second approach, we demonstrate for the first time highly-performant Localized GeOI pMOS devices down to 75 nm gate length, with controlled threshold voltage and drive current up to 600 muA/m@-1.1 V. We show a +35% improvement in drive current compared to Si references for the same Gate overdrive.

First demonstration of ultrathin body c-SiGe channel FDSOI pMOSFETs combined with SiGe(:B) RSD: Drastic improvement of electrostatics (V th,p tuning, DIBL) and transport (μ 0 , I sat ) properties down to 23nm gate length

We hereby present for the first time a successful integration of ultrathin (3.2nm) c-Si<inf>0.8</inf>Ge<inf>0.2</inf> layers in Fully Depleted (FD) SOI pMOSFETs (total body thickness: 7.8nm) combined with Si<inf>0.7</inf>Ge<inf>0.3</inf>(:B) Raised Source-Drain. Comparisons with SOI devices show that the c-Si<inf>0.8</inf>Ge<inf>0.2</inf>/SOI channels enable to tune the threshold voltage by +120mV (with excellent variability performance A<inf>Vt</inf>=1.47mV.µm) without SCE or DIBL degradation (60mV/V @ L=23nm). Moreover c-Si<inf>0.8</inf>Ge<inf>0.2</inf>/SOI combined with Si<inf>0.7</inf>Ge<inf>0.3</inf>(:B) RSD leads to significant gain in Access resistance (−60%), transconductance and I<inf>sat</inf> (+170% & +220% @ L=23nm).

Study of piezoresistive properties of advanced CMOS transistors: Thin film SOI, SiGe/SOI, unstrained and strained Tri-Gate Nanowires

We hereby present an exhaustive extraction and study of piezoresitive (PR) coefficients in advanced CMOS transistors. In particular, we have evidenced the dependence with channel thickness and channel material compositions (SiGe with various Ge contents). Moreover we report for the first time the measurement of PR coefficient on uniaxially strained and unstrained Tri-Gate Nanowires transistors.

Dual Strained Channel co-integration into CMOS, RO and SRAM cells on FDSOI down to 17nm gate length

We hereby present for the first time a successful Dual Strained Channel On Insulator (DSCOI) planar co-integration of tensily strained SOI nFETs and compressively strained SiGe pFETs down to 17nm gate length with functional ring oscillators and 6T SRAM cells. Various Ge contents and growth templates (unstrained or strained SOI) were screened in order to optimize the trade-off between threshold voltage adjustment with a single metal gate and strain-induced mobility enhancement. In particular, we reach 106% mobility boost for nFETs on sSOI and 70% for co-integrated pFETs on Si0.6Ge0.4/sSOI, compared to SOI (Eeff=0.6MV/cm). Moreover, the symmetrically low Vth,n and Vth,p result in −39% propagation delays improvement compared to SOI at 0.9V supply voltage.

Dual metallic source and drain integration on planar Single and Double Gate SOI CMOS down to 20nm: Performance and scalability assessment

We hereby report the fabrication, electrical characterization and TCAD simulation of planar Single and Double Gate n-and p-MOSFETs with metallic Dopant Segregated Source and Drain (DSS) on SOI, with gate lengths down to 20nm. A wide range of experimental data for various device architectures (Single Gate, Single Gate on Ultra Thin Buried Oxide, Double Gate), S/D metallizations (Pt, Ni, Er, Yb), and doping conditions at the S/D-channel interfaces are analyzed in order to evaluate the trade-off between performance and Short-Channel Effects (SCE) control of metallic S/D MOSFETs for the sub-22nm nodes. We demonstrate pFET devices with promising electrical behavior (ION=790µA/µm; IOFF=60nA/µm @ VDS=-1.2V; Lg=30nm), suitable for high performance applications. Excellent SCE control is also reported down to 30nm (DIBL=50mV/V), through the use of Double Gate transistors.