P. Perreau

Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic V<inf>T</inf>-variability performances are obtained (A<inf>VT</inf>=1.45mV.µm). This leads to 6T-SRAM cells with good characteristics down to V<inf>DD</inf>=0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σ<inf>SNM</inf><SNM/6) down to V<inf>DD</inf>=0.7V. We also demonstrate ultra-low leakage (<0.5pA/µm) on UT2B devices at L<inf>G</inf>= 30nm by source/back biasing thanks to a low gate current and Gate Induced Drain Lowering (GIDL).

Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

Recent device developments and achievements have demonstrated that planar undoped channel Fully depleted SOI devices are becoming a serious alternative to Bulk technologies for 20nm node and below. We have proven this planar option to be easier to integrate than the non planar devices like FinFET. This paper gives an overview of the main advantages provided by this technology, as well as the key challenges that need to be addressed. Electrostatic integrity, drivability, within wafer variability and scalability are addressed through silicon data (down to 18nm gate length) and TCAD analyses. Solutions to the Multiple VT challenges and non logic devices (ESD, I/Os) are also reported.

Efficient multi-V T FDSOI technology with UTBOX for low power circuit design

For the first time, Multi-V<inf>T</inf> UTBOX-FDSOI technology for low power applications is demonstrated. We highlight the effectiveness of back biasing for short devices in order to achieve I<inf>ON</inf> current improvement by 45% for LVT options at an I<inf>OFF</inf> current of 23nA/µm and a leakage reduction by 2 decades for the HVT one. In addition, fully functional 0.299um² bitcells with 290mV SNM at 1.1V and Vb=0V operation were obtained. We also demonstrate on ring oscillators and 0.299µm² SRAM bitcells the effectiveness (ΔV<inf>T</inf> versus V<inf>b</inf> ∼ 208mV/V) of the conventional bulk reverse and forward back biasing approaches to manage the circuit static power and the dynamic performances.

Work-function engineering in gate first technology for multi-V T dual-gate FDSOI CMOS on UTBOX

For the first time, we demonstrate low-V<inf>T</inf> (V<inf>Tlin</inf> ±0.32V) nMOS and pMOS adjusted in a gate first FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for low-V<inf>T</inf> pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune the work-function above midgap while maintaining good reliability and mobility. Short channel performance of 500µA/µm I<inf>ON</inf> and 245µA/µm I<inf>EFF</inf> at 2nA/µm I<inf>OFF</inf> and V<inf>DD</inf>=0.9V is reported on pMOS with a TaAlN gate. In addition, it is found that the combination of these two metal gates with either n- or p-doped ground planes below the Ultra-Thin Buried Oxide (BOX) can offer 4 different V<inf>T</inf> from 0.32V to 0.6V for both nMOS and pMOS, demonstrating a real multiple-V<inf>T</inf> capability for FDSOI CMOS while keeping the channel undoped and the V<inf>T</inf> variability around A<inf>VT</inf>=1.3mV.µm.

Drain current variability and MOSFET parameters correlations in planar FDSOI technology

We present for the first time an extensive experimental study of the statistical variability of the drain current (I<inf>D</inf>) in 6nm thin undoped Silicon-On-Insulator (SOI) MOSFETs. I<inf>D</inf> variations (σ<inf>ID</inf>) are found to be highly correlated with both threshold voltage (V<inf>T</inf>) and ON-state resistance (R<inf>ON</inf>) fluctuations. Their respective contributions cannot be directly added to capture σ<inf>ID</inf> because of an advantageous ΔV<inf>T</inf>/ΔR<inf>ON</inf> correlation. Taking into account such correlations is of great interest for an accurate definition of spice model corners. We also evidence the main technological sources of I<inf>D</inf> fluctuation. Improving the access resistances (R<inf>SD</inf>) enables to lowering the R<inf>ON</inf> variability. Engineering of the source/drain implantations (Low temperature C+P co-implant) mainly reduces the current (I<inf>SAT</inf>, I<inf>OFF</inf>) variability through an improved V<inf>T</inf> control.

Low power UTBOX and back plane (BP) FDSOI technology for 32nm node and below

This paper highlights the interest of FD-SOI with high-k and metal gate as a possible candidate for low power multimedia technology. The possibility of multi-VT by combining UTBOX with back plane, back biasing, variable TiN thickness and Al2O3 in the gate stack is demonstrated. The viability of these approaches is corroborated via mobility and reliability measurements. Dual gate oxide co-integrated devices are reported. The effectiveness of back biasing for short devices is demonstrated through ring oscillators and 0.299µm² SRAM bitcells performance reflecting that the conventional bulk reverse and forward back biasing approaches to manage the circuit static power and the dynamic performances are fully compatible with FDSOI. Finally, thanks to a hybrid FDSOI/bulk co-integration with UTBOX all IPs required in a SOC could be demonstrated for LP applications.

Planar FDSOI technology for sub 22nm nodes

Recent device developments and achievements have shown that undoped channel planar Fully depleted SOI devices are becoming a serious alternative to Bulk technologies for 22nm node and below. This planar option seems to be even easier than non planar FinFET devices. This paper will report the main results obtained with this technology and will compare these results with the state of the art of Bulk and FinFET technologies: electrostatic performance, drivability, variability and scalability will be presented through silicon data and TCAD analysis. Challenges with respect to Multiple VT aspects and SRAM will also be reported.

New insight on V T stability of HK/MG stacks with scaling in 30nm FDSOI technology

In this paper it is shown that HfO2 and HfZrO oxides suffer from large VT instabilities, up to 230mV, when the device width (W) is scaled down to 80nm. It is explained by undesirable lateral oxygen diffusion through the spacers, which mainly modifies the metal workfunction in narrow transistors. HfSiO(N) oxides exhibit a much better immunity to this effect, attributed to a different crystallinity of the HK layer. Moreover, Al incorporation in the gate stack hardly changes the VT stability.

UTBOX and ground plane combined with Al 2 O 3 inserted in TiN gate for V T modulation in fully-depleted SOI CMOS transistors

Thin film devices (FDSOI) are among the most promising candidates for next device generations due to their better immunity to short channel effects (SCE). In addition, the introduction of high-k and metal gate has greatly improved the MOSFETs performance by reducing the electrical oxide thickness (CET) and gate leakage current. However, if midgap metal gate is sufficient to provide a high symmetrical threshold voltage (VT∼0.45V) for both NMOS and PMOS devices [1], still one major challenge is to provide VT modulation with an undoped channel in order to satisfy the low power (LP) circuit design requirements [2–5]. To overcome this issue, combining UTBOX substrate with ground plane (GP) has been proposed [2,5]. However this technique with midgap metal gate requires a FBB biasing in order to realize low VT thats implies a disruptive circuits design to avoid forward diode biasing in the substrate between the two opposite GP type beneath the BOX [6]. In order to introduce more VT modulation flexibilities and especially for LVT PMOS and HVT NMOS, aluminum Oxide (Al2O3) inserted in TiN gate stack has been proposed for bulk devices [7–8] in a gate first process. The viability of this option is studied in this paper for FDSOI, for HfO2 and HfSiON gate oxide, through transistors performance, reliability and variability analysis.