D. Fleury

Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling

A new mobility degradation specific to short channel MOSFETs is studied and elucidated. Pocket implants/dopants pile-up, interface states/oxide charges, remote Coulomb scattering or ballisticity are insufficient to explain this degradation. The role of non-Coulombian (neutral) defects, which can be healed by increasing the annealing temperature, is evidenced

Advances in 3D CMOS sequential integration

For the first time 3D sequential CMOS integration turns up to be an actual competitor for sub 22nm technology nodes. Thanks to the original use of molecular bonding, high quality top Si active layers are obtained. Thermally robust bottom salicide goes through the whole top FET processing without any significant sheet resistance degradation. The low temperature integration of raised source and drain for top layers is demonstrated. A decrease by 4Å of the Equivalent Oxide Thickness is measured when a low thermal budget process is implemented. The electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm. It leads to a threshold voltage dynamic shift of 130mV enabling SRAM stabilization.

A New Technique to Extract the Source/Drain Series Resistance of MOSFETs

This letter demonstrates a new technique to extract the source/drain series resistance of MOSFETs. Unlike the well-known total resistance techniques, Rsd is extracted in a way that the result is insensitive to effective length and mobility variations. The technique has been successfully applied to 45-nm bulk and fully depleted SOI MOSFETs with high-κ and metal gate, having channel length down to 22 nm. The technique provides a high accuracy and allows fast measurements and statistical analysis.

New Y-function-based methodology for accurate extraction of electrical parameters on nano-scaled MOSFETs

We developed a new Y-function-based extraction methodology to overcome the difficulties encountered by applying the conventional techniques. Our method relies on a robust recursive algorithm which requires a limited number of input parameters on which the results have a weak dependence, and so an increased reliability. The obtained results are in line with the previous methods, but show an improved accuracy. Finally, parameter extraction performed through this technique has provided accurate and reliable results over a large range of MOSFET architectures.

Automatic Extraction Methodology for Accurate Measurements of Effective Channel Length on 65-nm MOSFET Technology and Below

The length of MOSFET channels is an important circuit design parameter, and this paper focuses on a new industrially-compatible technique using gate-to-channel measurements Cgc(Vg) to provide accurate extraction of the channel length. Thanks to fully-automatic probers, the technique provides large scale extractions and so, statistical-based results can be extracted with a maximized reliability. An in-depth study of parasitic capacitances has been performed to improve the extraction accuracy to within a few nanometers.

A new technique to extract the gate bias dependent s/d series resistance of sub-100nm MOSFETs

In this study, a new technique to extract the S/D series resistance (R<inf>sd</inf>) from the total resistance versus transconductance gain plot R<inf>tot</inf>(1/β) is proposed. The technique only requires the measurement of I<inf>d</inf>(V<inf>gs</inf>)|<inf>Vgt</inf> and β, allowing fast and statistical analysis in an industrial context. Unlike the usual R<inf>tot</inf>(L)-based techniques, it has the advantage of being insensitive to the channel length and mobility variations and finally enables to extract very accurate values for R<inf>sd</inf>(V<inf>gs</inf>) and the effective mobility reduction factor µ<inf>eff</inf>(V<inf>gt</inf>)/µ<inf>eff</inf>(0).

Planar Bulk + technology using TiN/Hf-based gate stack for low power applications

This work highlights the new bulk⁺ technology using high-K dielectric, single metal gate and fully depleted SON (silicon on nothing) channel for sub-45 nm low cost applications. Thin silicon channel (down to T_si= 8 nm) and thin BOX (T_box = 15 to 25 nm) are obtained using the SON process (Jurczak, 1999). Transistor performance (W_design/L_gate= 90 nm/40 nm) at V_dd = 1.1 V and I_off < 2 nA/ mum is as high as 1298 muA/ mum for nMOS and 663 muA/ mum for pMOS. In addition, reliability, noise and 6T-SRAM bit cells down to 0.249 mum² are characterized. Significant improvements with respect to conventional bulk technology are demonstrated.

First CMOS integration of ultra thin body and BOX (UTB 2 ) structures on bulk direct silicon bonded (DSB) wafer with multi-surface orientations

For the first time we demonstrate the CMOS integration of undoped fully-depleted Ultra Thin Body and BOX devices (UTB2) with (110)/(100) substrate crystal orientation for pFET and nFET respectively. For this, we used an original 3D-folded Bulk+/Silicon-On-Nothing (SON) process on DSB substrate. Resulting multi-surface orientations devices are studied.

Gate-All-Around technology: taking advantage of ballistic transport ?

This work presents an experimental study in order to evaluate the quality of transport in state-of-the-art Gate-All-Around devices. 25nm×20nm×10nm (LxWxT Si ) silicon channel devices with metal/high-k gate all-round stack were characterized electrically in terms of mobility and limiting velocity in order to evaluate the possible occurrence of ballisticity. Conclusions are finally presented in the scope of elementary circuit perspectives.