C. M. Ng

Inducing ferromagnetism in ZnO through doping of nonmagnetic elements

In this work, Zn, Al, Pt, Ag, and Au nonmagnetic metallic films were deposited on the surface of ZnO film, followed by high vacuum annealing at different temperatures. Results showed that (Zn,Al,Pt)∕ZnO films possessed room temperature ferromagnetism (RTF) after the vacuum annealing, while (Ag,Au)∕ZnO films did not. Our detailed structural investigations (transmission electron microscopy and x-ray photoelectron spectroscopy) revealed that this RTF was associated with the presence of metal clusters. The RTF disappeared in Al∕ZnO after a subsequent annealing in air, as metal clusters were oxidized. Pt∕ZnO remained ferromagnetic, as the metal cluster structure was stable subjected to the air annealing.

Mechanism of room temperature ferromagnetism in ZnO doped with Al

ZnO recently receives extensive interest owing to its potential applications in the dilute magnetic semiconductor. In this work, Al was deposited onto the surface of ZnO film followed by high vacuum annealing. The film showed the room temperature ferromagnetism (RTF). The saturation magnetization (Ms) highly depends on both the thickness of the Al top layer and the thickness of the ZnO film. The RTF disappeared when the film was further annealed in air atmosphere. The detailed structure characterizations (x-ray diffraction and x-ray photoelectron spectroscopy) revealed that the RTF was associated with a charge transfer between Al and Zn.

Effects of thermal annealing on the band alignment of lanthanum aluminate on silicon investigated by x-ray photoelectron spectroscopy

In this work, we investigate the changes in the band offsets of lanthanum aluminate on silicon after postdeposition annealing at 600 and 800 °C by x-ray photoelectron spectroscopy (XPS). It is found that annealing at 800 °C reduces the conduction band offset from 2.31 to 1.39±0.2 eV. A detailed analysis is performed to ascertain the origin of the changes. We will show that the observed band offset changes are not a consequence of alterations in the bulk properties of the oxide film, but rather a true band alignment change between the two materials. After systematically considering “artefacts” of XPS measurements, including extra-atomic relaxation and differential charging, we conclude that the band offset changes originate mainly from an interfacial effect. While intrinsic gap states dipoles are not sufficient to account for the large band offset shifts, we turned our attention to examine the interface of the gate oxide stack. We show the existence of at least two types of dipoles. One of the dipoles exis...

A low-cost method of forming epitaxy SiGe on Si substrate by laser annealing

In this letter, a low-cost alternative for forming high grade silicon germanium (SiGe) by a laser-induced crystallization of an amorphous Ge layer deposited directly on Si+ preamorphized implantation Si substrate is demonstrated. The results show that a fully strained epitaxial SiGe layer on the Si (100) substrate can be obtained at laser fluence above the epitaxial threshold. This is due to a liquid-phase epitaxial regrowth process of the laser annealing induced melted layer. Below the epitaxial threshold, polycrystalline SiGe is formed due to explosive recrystallization process. Simultaneous boron activation is achieved with the SiGe formation, a result due to the high temperature induced by the laser annealing.

Improvement of Negative Bias Temperature Instability by Stress Proximity Technique

The stress proximity technique (SPT) is found to improve negative bias temperature instability (NBTI) in p-channel metal-oxide-semiconductor field-effect transistors significantly. A first-principles calculation is carried out to examine the effect of strain on NBTI, and a process simulation is conducted to determine the change in stress profile in the device induced by SPT. The first-principles calculation shows that a larger strain leads to higher NBTI degradation. On the other hand, the process simulation shows that, although the compressive stress along the channel direction is enhanced by SPT, the vertical tensile stress is greatly reduced by SPT. The larger reduction in stress along the vertical direction is believed to be responsible for the improvement of NBTI by SPT.

Ultra‐Shallow Junction Formation—Physics and Advanced Technology

In this paper, the advanced technology in the ultra‐shallow junction formation and its physical understanding for sub‐nano CMOS devices are presented. After quickly presenting the device issues for the next generation of CMOS devices, we shall focus on the formation of highly activated Ultra‐Shallow Source Drain extension. In fact, the formation of ultra‐shallow junctions (USJ) for future integrated circuit technologies requires achieving high activation levels and abrupt profiles. To achieve the challenging targets set out in the semiconductor roadmap, it is crucial to reach a much better understanding of the basic physical processes taking place during USJ processing. Subsequently, we review current understanding of dopant‐defect interactions during thermal processing of device structures—interactions which are at the heart of the dopant diffusion and activation anomalies seen in USJ leading to device performance degradation. Based on the physical understanding, we shall review and discuss some promisin...

Laser annealing induced high Ge concentration epitaxial SiGe layer in Si1−xGex virtual substrate

Graded silicon germanium (Si1−yGey) epilayer with a thin layer of high Ge concentration (∼36%) near the surface is obtained by laser thermal annealing (LTA). The graded Si1−yGey layer is formed during a liquid phase regrowth after LTA. The relaxation in this graded Si1−yGey epilayer is insignificant; therefore it can be integrated into the source/drain of the p-type metal-oxide-semiconductor field effect transistor to induce high compressive strain to the Si channel. The thickness of the graded Si1−yGey epilayer and the concentration of the Ge near the surface can be controlled by the laser fluence, which in turn changes the strain induced to the Si channel of strained devices.

Influence of hydrogen dispersive diffusion in nitrided gate oxide on negative bias temperature instability

Influence of hydrogen dispersive diffusion in nitrided gate oxide on negative bias temperature instability (NBTI) is examined by using the analytical reaction-dispersive-diffusion (RDD) model, which was developed within a framework of the classical reaction-diffusion model by incorporating the dispersive transport nature of the diffusion. The NBTI experiments verify that by taking the dispersive transport into account, the RDD model well describes the NBTI degradation including its dependence on the stress time, stress temperature and interfacial nitrogen concentration and its power-law behaviors as well. This in turn gives an insight into the roles of the hydrogen dispersive diffusion in the NBTI process.

Vacancy engineering by optimized laser irradiation in boron-implanted, preamorphized silicon substrate

In this letter, the effect of vacancies generated by preirradiated laser on dopant diffusion and activation in preamorphized silicon substrate has been studied. Laser-induced melting in silicon was used to generate excess vacancies near the maximum melt depth before silicon substrate amorphization and subsequent boron implantation. We demonstrate that by matching the preirradiated laser melt depth with the implant amorphize depth, it can effectively reduce the silicon self-interstitials released from the end-of-range defect band. The results show great suppression in boron transient enhanced diffusion and significant removal of end-of-range defects. This is attributed to the recombination of laser-generated excess vacancies with preamorphizing induced free silicon interstitials at the end-of-range region.

Three Dimensional (3D) n-gate MOSFET

The concept of a three-dimensional (3D) n-gate MOSFET device SOI substrate has been proposed and developed in this work. This device consists of a rounded surface channel with gate extensions into the buried oxide for improved subthreshold behavior. The fabrication steps are compatible with the bulk CMOS process and it requires a mere addition of a reactive ion etching (RIE) etch step. Hence, the proposed n-gate transistor can be a viable replacement for bulk transistor in the near future.