F. Benistant

A novel CMOS compatible L-shaped impact-ionization MOS (LI-MOS) transistor

This paper reports a novel L-shaped impact-ionization MOS (LI-MOS) transistor technology that achieves subthreshold swing well below 60 mV/decade at room temperature. First, the LI-MOS transistor is CMOS process compatible, and requires little process modification for integration in a manufacturable process. Second, the LI-MOS structure employs raised source/drain (S/D) regions that enable controllability and scalability of the impact ionization region (I-region). Third, the LI-MOS has superior compactness over previously reported I-MOS device structures. Fourth, the LI-MOS enables the integration of novel materials for band gap and strain engineering to enhance the impact ionization rate in the I-region. Based on the above technology, we demonstrate a record subthreshold swing of 4.5 mV/decade at room temperature for a 100 run gate length device that incorporates a SiGe I-region. The smallest impact-ionization-based MOS device with a gate length of 60 nm is also demonstrated with a subthreshold swing that is well below 60 mV/decade

Comprehensive model of damage accumulation in silicon

Ion implantation induced damage accumulation is crucial to the simulation of silicon processing. We present a physically based damage accumulation model, implemented in a nonlattice atomistic kinetic Monte Carlo simulator, that can simulate a diverse range of interesting experimental observations. The model is able to reproduce the ion-mass dependent silicon amorphous-crystalline transition temperature of a range of ions from C to Xe, the amorphous layer thickness for a range of amorphizing implants, the superlinear increase in damage accumulation with dose, and the two-layered damage distribution observed along the path of a high-energy ion. In addition, this model is able to distinguish between dynamic annealing and post-cryogenic implantation annealing, whereby dynamic annealing is more effective in removing damage than post-cryogenic implantation annealing at the same temperature.

Ultra‐Shallow Junction Formation—Physics and Advanced Technology

In this paper, the advanced technology in the ultra‐shallow junction formation and its physical understanding for sub‐nano CMOS devices are presented. After quickly presenting the device issues for the next generation of CMOS devices, we shall focus on the formation of highly activated Ultra‐Shallow Source Drain extension. In fact, the formation of ultra‐shallow junctions (USJ) for future integrated circuit technologies requires achieving high activation levels and abrupt profiles. To achieve the challenging targets set out in the semiconductor roadmap, it is crucial to reach a much better understanding of the basic physical processes taking place during USJ processing. Subsequently, we review current understanding of dopant‐defect interactions during thermal processing of device structures—interactions which are at the heart of the dopant diffusion and activation anomalies seen in USJ leading to device performance degradation. Based on the physical understanding, we shall review and discuss some promisin...

SDODEL MOSFET for performance enhancement

A high-energy, low-dose implant of the source/drain (S/D) doping type is introduced after the gate definition step to form doped regions beneath and separated from the source and drain regions to fabricate source/drain on depletion layer (SDODEL) transistors. Under zero bias, these doped regions are fully depleted and the resulting transistor structure is termed an SDODEL MOSFET. The fully depleted regions act electrically like insulators, as in the case of silicon-on-insulator (SOI), to reduce junction capacitance. SDODEL MOSFETs with 0.16-/spl mu/m gate length are fabricated by a slightly modified CMOS process without any additional masking steps. Subthreshold slope, simulated threshold voltage V/sub t/ rolloff, and off-state leakage I/sub off/ are comparable with control devices. The junction capacitance in SDODEL MOSFETs is found to be reduced by more than 40% compared to conventional MOSFETs. Measurement of ring oscillator speeds demonstrates that SDODEL MOSFETs enable a 15% reduction in gate delay t/sub d/ for each inverter stage. SDODEL transistors provide a low-cost alternative to SOI for reduction of S/D junction capacitance.

Application of molecular dynamics for low-energy ion implantation in crystalline silicon

Molecular dynamics (MD) is set to replace Monte Carlo (MC) methods utilizing the binary collision approximation (BCA) in modeling dopant distributions after ion implantation in the low energy regime. Simultaneous nonbinary interactions come into play as the ion slows down; unlike BCA, MD automatically accounts for multiple collisions between ion and its neighboring atoms. In this work, the energy limit below which BCA fails is estimated from density functional theory (DFT) calculations for a wide range of dopants. Impurity profiles are generated using the MD code, MDRANGE. A database consisting of secondary ion mass spectrometry (SIMS) profiles covering a wide range of dopants (B, C, F, N, P, As, Ge, In, and Sb) over the energy regime of 0.5–10keV at critical channeling directions have been set up. The MD simulated profiles show good agreement with SIMS data, which have been obtained either with a quadrupole—or magnetic-sector—based mass spectrometer.

Phosphorus Implant For S/D Extension Formation: Diffusion And Activation Study After Spacer And Spike Anneal

Formation of highly activated S/D extension is one of the key issues to meet the requirements for further downscaling of CMOS devices. Germanium‐preamorphization implant (Ge‐PAI) followed by solid phase epitaxial regrowth (SPER) is capable of forming abrupt and shallow junctions with activation levels well above solid solubility. In this paper, we demonstrate a possible alternative by using phosphorus (P) with the Ge‐PAI and boron (B) Halo implant to form the S/D extension of NMOS. The anomalous diffusion and activation of P after the conventional spacer and spike anneals were studied. We observed that a highly activated and shallow junction can be formed via Ge‐PAI after spacer anneal which is equivalent to a low temperature SPER. The level of P activation is enhanced even more when B Halo is considered. It is postulated that this is due to the competing interactions of B and P with the emitted interstitials of the end‐of‐range (EOR) defects. However, improvement in junction depth and electrical properti...

Analytical damage tables for crystalline silicon

Tables describing the damage profiles created after ion implantation are presented for a wide range of impurities at three tilts and twists (7°/22°, 0°/0°, and 45°/45°), showing the tilt and rotational effects on the damage profiles. While postimplantation damage is well understood in amorphous silicon, damage tables suitable for crystalline silicon, in which channeling effects are dominant, were not yet available. The impurities of concern are B, C, P, N, F, Si, As, Ga, Ge, In, and Sb. Energy ranges from 0.1 to 1000 keV. The Monte Carlo simulations are performed by the binary collision code CRYSTAL-TRIM implemented in DIOS utilizing its full cascade capability. The coefficients are extracted by a technique, called sampling calibration of profiles, which allows any damage profiles between two energies to be predicted by interpolation. This technique overcomes the limitations plaguing some of the most common analytical impurity and damage models.

An Extensive Study on the Boron Junctions Formed by Optimized Pre‐Spike/Multiple‐Pulse Flash Lamp Annealing Schemes: Junction Formation, Stability and Leakage

In this work, the electrical activation of Boron in Germanium pre‐amorphized silicon substrate upon flash lamp annealing (FLA) is investigated. We demonstrate that FLA helps in the reduction of the EOR defects, resulting in minimal transient enhanced diffusion and dopant deactivation effect. It has also been observed that the junction stability improves with the increasing number of flash pulses, which is clearly reflected by the dopant deactivation level upon post‐thermal treatment. In another FLA scheme, the spike rapid thermal annealing (RTA) performed prior to the flash further enhances the junction stability. However, this pre‐spike RTA step induces extensive dopant diffusion and an overall degradation in sheet resistance. The above observations are concluded to be due to the different extent of silicon interstitial supersaturation that can be explained by the interactions between the extended defects and dopants. Lastly, leakage current for the junctions formed under different FLA schemes are compar...

The Impact of Boron Halo on Phosphorus Junction Formation and Stability

In this paper we study the diffusion and activation behaviors of ultrashallow and high concentration of phosphorus (P) dopants in silicon processed with low-temperature thermal annealing. For the first time, significant improvement in dopant activation is observed when a boron halo implant is incorporated in the germanium preamorphized P junction. Our results are discussed in terms of the interactions between dopants and the point defects upon annealing. In addition, no rapid deactivation behavior is observed for the P-doped junction during the isochronal annealing cycle.