C. P. Ho

VLSI Process modeling—SUPREM III

Over the past several years, the process-simulation tool SUPREM II has proven useful in the design and optimization of both bipolar and MOS technologies. This paper describes a new and significantly more capable version of the program--SUPREM III--which incorporates process models suitable for VLSI device design. This new version of the program is now generally available and should provide a powerful new tool in VLSI design. For the first time, the program models multilayer structures (up to five material layers). It also incorporates substantially upgraded diffusion, oxidation, ion implantation, and other process models. These models incorporate, where possible, recent thinking about underlying physical mechanisms. The program remains a one-dimensional simulator; extensions to two dimensions are discussed. This paper concentrates on the process models and their underlying physics; implementation issues are addressed elsewhere.

Si / SiO2 Interface Oxidation Kinetics: A Physical Model for the Influence of High Substrate Doping Levels I . Theory

A physical model based on the statistics of silicon point defects is proposed to explain the commonly observed enhanced oxidation rates of heavily doped silicon. The physical effect of the high doping levels on the interface oxidation kinetics is postulated to be primarily electrical in nature. The high doping levels shift the position of the Fermi level toward the conduction band (n‐type) or toward the valence band (p‐type) even at oxidation temperatures, causing an increase in the equilibrium concentration of point defects (vacancies) in the silicon substrate. These point defects may provide reaction sites for the chemical reaction converting Si to and thereby increase the rate at which this reaction occurs. This paper describes the theoretical basis for this model and predicts quantitatively the expected oxidation rates for n+‐ and p+‐doped silicon under a wide range of oxidation conditions.

Improved MOS device performance through the enhanced oxidation of heavily doped n + silicon

The thermal oxidation of heavily doped silicon is well known to produce faster oxidation kinetics than lightly doped silicon. The physical mechanism responsible for this is reviewed, and quantitative data are presented which demonstrate that the effect is most pronounced over n+regions on substrates, oxidized at low temperatures in an H2O ambient. Understanding of this phenomenon allows it to be applied to a wide variety of technologies and device structures in which improved device performance is achieved simply through optimization of oxidation conditions. Specific examples of this improvement are described for NMOS and DMOS structures. Utilization of phenomena such as the one described here becomes increasingly important as devices and technology are pushed toward ultimate physical limits.

Experimental determination of the temperature dependence of argon annealed fixed oxide charge at the Si/SiO2 interface

Fixed oxide charge density Nf at the Si/SiO2 interface for (100) and (111) wafers oxidized in dry O2 and annealed in argon has been studied as a function of the Ar anneal temperature. In contrast to previous qualitative results, the annealed Nf value was found to be dependent on the anneal temperature. Wafers thermally cycled in Ar between different temperatures showed reproducible, steady state Nf values which also cycled with temperature. These results may indicate that residual charge densities after annealing represent an equilibrium state of the Si/SiO2 interface.

WP-A6 thermal oxidation of heavily doped silicon: Physical modeling and device applications

region and cross the sidewall of the emitter-base juncticm. No evidence was found for penetration of dislocations i r to the bottom-wall of the emitter-base junction at the depth of 1.1 pm. The mitter-base junction characteristics were degraded in the 0 transistors as compared to the transistors treated through dry N2 ambient (designated as N). The reverse leakege current averaged over 100 samples was an order of magnitu(:le higher and the spread in current values was greater in the 10 transistors. The incidence of random, high-amplitude, lowfrequency noise pulses, popcorn noise, was greater. We believe that the degradation in characteristics is due to the penetration of the dislocations into the sidewall of the emittctrbase junction.