C. Perrot

Efficient multi-V T FDSOI technology with UTBOX for low power circuit design

For the first time, Multi-V<inf>T</inf> UTBOX-FDSOI technology for low power applications is demonstrated. We highlight the effectiveness of back biasing for short devices in order to achieve I<inf>ON</inf> current improvement by 45% for LVT options at an I<inf>OFF</inf> current of 23nA/µm and a leakage reduction by 2 decades for the HVT one. In addition, fully functional 0.299um² bitcells with 290mV SNM at 1.1V and Vb=0V operation were obtained. We also demonstrate on ring oscillators and 0.299µm² SRAM bitcells the effectiveness (ΔV<inf>T</inf> versus V<inf>b</inf> ∼ 208mV/V) of the conventional bulk reverse and forward back biasing approaches to manage the circuit static power and the dynamic performances.

Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology

In this paper, we present FD-SOI with High-K and Single Metal gate as a possible candidate for LP multimedia technology. Dual gate oxide co-integrated devices with EOT 17Å/Vdd 1.1V and 29Å/Vdd 1.8V are reported. The interest of Ultra-Thin Buried Oxide substrates (UTBOX) is reported in term of Multiple Vt achievement and matching improvement. Delay improvement up to 15% is reported on Ring Oscillators as compared to bulk 45nm devices. In addition, for the first time 99.998% 2Mbit 0.374µm2 SRAM cut functionality has been demonstrated. Thanks to a hybrid FDSOI/bulk co-integration with UTBOX all IPs required in a SOC are demonstrated for LP applications.

Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below

In this paper we explore for the first time the impact of an Ultra-Thin BOX (UTBOX) with and without Ground Plane (GP) on a 32nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50mV DIBL reduction by using 10nm BOX thickness for NMOS and PMOS devices at 33nm gate length. Moreover, the combination of DIBL reduction and threshold voltage modulation by adding GP enables to reduce the Isb current by a factor 2.8 on a 0.299µm2 SRAM cell while maintaining an SNM of 296mV @ Vdd 1.1V.

Reliable 3D damascene MIM architecture embedded into Cu interconnect for a Ta 2 O 5 capacitor record density of 17 fF/μm 2

A new simple 3D Damascene architecture requiring only one additional mask is introduced for high-density MIM capacitors. TiN/Ta₂O₅/TiN stack deposited by PEALD has been integrated between Cu interconnect levels to maximize quality factor Q, reaching up to 17 fF/μm² capacitance. High-performance, breakdown voltages over 15 V and good linearity, C₁ = 76 ppm/V and C₂ = 63 ppm/V² at 100 kHz, make this capacitor an unique solution for analog and RF applications embedded in Cu BEOL.

Impact of TaN/Ta copper barrier on full PEALD TiN/Ta2O5/TiN 3D damascene MIM capacitor performance

MIM capacitors are widely integrated for RF and analog applications. A high density full PEALD TiN/Ta2O5/TiN capacitor is integrated among copper interconnect following an innovative 3D damascene architecture. The impact of a TaN/Ta layer, introduced to avoid Cu diffusion, on both TiN electrode properties and integrated MIM stack performance is studied. Unexpected lower current was obtained without the barrier layer. As a result, up to 17 fF/mum2 capacitance densities were achieved with breakdown voltage over 15 V and excellent voltage linearity.

UTBOX and ground plane combined with Al 2 O 3 inserted in TiN gate for V T modulation in fully-depleted SOI CMOS transistors

Thin film devices (FDSOI) are among the most promising candidates for next device generations due to their better immunity to short channel effects (SCE). In addition, the introduction of high-k and metal gate has greatly improved the MOSFETs performance by reducing the electrical oxide thickness (CET) and gate leakage current. However, if midgap metal gate is sufficient to provide a high symmetrical threshold voltage (VT∼0.45V) for both NMOS and PMOS devices [1], still one major challenge is to provide VT modulation with an undoped channel in order to satisfy the low power (LP) circuit design requirements [2–5]. To overcome this issue, combining UTBOX substrate with ground plane (GP) has been proposed [2,5]. However this technique with midgap metal gate requires a FBB biasing in order to realize low VT thats implies a disruptive circuits design to avoid forward diode biasing in the substrate between the two opposite GP type beneath the BOX [6]. In order to introduce more VT modulation flexibilities and especially for LVT PMOS and HVT NMOS, aluminum Oxide (Al2O3) inserted in TiN gate stack has been proposed for bulk devices [7–8] in a gate first process. The viability of this option is studied in this paper for FDSOI, for HfO2 and HfSiON gate oxide, through transistors performance, reliability and variability analysis.

Toward next high performances MIM generation: up to 30fF/μm 2 with 3D architecture and high-κ materials

This paper deals with the realization of new high performances metal-insulator-metal (MIM) capacitors. Using PEALD deposited HfO₂, ZrO₂, A1₂O₃ and their combination with Ta₂O₅, MIM stacks have been realized. By controlling high-κ deposition characteristics and dielectric stack architecture, state of the art electrical results for high performances analog design (weak non- linearity and sustaining high operating bias) are obtained. The use of 3D architecture allows combining such characteristics with very high capacitance density. A first realization with Ta₂O₅ leads to 30fF/mum² and demonstrates the interest of such an approach for next generation high performances MIM capacitors.