S. Denorme

Efficient multi-V T FDSOI technology with UTBOX for low power circuit design

For the first time, Multi-V<inf>T</inf> UTBOX-FDSOI technology for low power applications is demonstrated. We highlight the effectiveness of back biasing for short devices in order to achieve I<inf>ON</inf> current improvement by 45% for LVT options at an I<inf>OFF</inf> current of 23nA/µm and a leakage reduction by 2 decades for the HVT one. In addition, fully functional 0.299um² bitcells with 290mV SNM at 1.1V and Vb=0V operation were obtained. We also demonstrate on ring oscillators and 0.299µm² SRAM bitcells the effectiveness (ΔV<inf>T</inf> versus V<inf>b</inf> ∼ 208mV/V) of the conventional bulk reverse and forward back biasing approaches to manage the circuit static power and the dynamic performances.

Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology

In this paper, we present FD-SOI with High-K and Single Metal gate as a possible candidate for LP multimedia technology. Dual gate oxide co-integrated devices with EOT 17Å/Vdd 1.1V and 29Å/Vdd 1.8V are reported. The interest of Ultra-Thin Buried Oxide substrates (UTBOX) is reported in term of Multiple Vt achievement and matching improvement. Delay improvement up to 15% is reported on Ring Oscillators as compared to bulk 45nm devices. In addition, for the first time 99.998% 2Mbit 0.374µm2 SRAM cut functionality has been demonstrated. Thanks to a hybrid FDSOI/bulk co-integration with UTBOX all IPs required in a SOC are demonstrated for LP applications.

Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below

In this paper we explore for the first time the impact of an Ultra-Thin BOX (UTBOX) with and without Ground Plane (GP) on a 32nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50mV DIBL reduction by using 10nm BOX thickness for NMOS and PMOS devices at 33nm gate length. Moreover, the combination of DIBL reduction and threshold voltage modulation by adding GP enables to reduce the Isb current by a factor 2.8 on a 0.299µm2 SRAM cell while maintaining an SNM of 296mV @ Vdd 1.1V.

28nm advanced CMOS resistive RAM solution as embedded non-volatile memory

A back-end integrated Resistive Random Access Memory (ReRAM) (TiN/HfO2/Ti/TiN) in advanced 28nm CMOS process is evaluated. Significant operating margins and high performances identified at device level (read margin, low power set/reset, endurance and retention) are demonstrated to be significantly reduced on larger statistics, i.e. characterized within 1kbit arrays. The High Resistance State (HRS) dispersion, identified as a limiting factor, is modeled through the “tunneling barrier thickness” variation. The optimization through electrical condition tuning is discussed. A global overview of HfO2 material performances is assessed on statistical basis and projection for larger array integration is discussed.

FDSOI devices with thin BOX and ground plane integration for 32nm node and below

In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX thicknesses with or without ground plane (GP). With a simple High-k/Metal gate structure, the 32 nm devices exhibits Ion/Ioff performances well situated for low power (LP) applications. The different BOX thicknesses and ground plane conditions are compared with bulk shrunk technology in terms of variability and noise. 0.499 mum2 SRAM cell has been characterized with less than 50 pA of standby current/cell and a SNM of 210 mV @ Vdd 1V.

Benefit of Al 2 O 3 /HfO 2 bilayer for BEOL RRAM integration through 16kb memory cut characterization

In this paper, for the first time, the reliability of HfO₂-based RRAM devices integrated in an advanced 28nm CMOS 16kbit demonstrator is presented. The effect of the introduction of a thin Al₂O₃ layer in TiN/Ti/HfO₂/Al₂O₃/TiN is explored to improve the memory performances. Thanks to the in-depth electrical characterization of both HfO₂ and HfO₂/Al₂O₃ stacks at device level and in the 16×1kbit demonstrator the interest of the bilayer is put forward (endurance: 1 decade after 1M cycles and retention: 6 hours at 200°C). Finally, thanks to our 3D model based on calculation of the Conductive Filament resistance using trap assisted tunneling (TAT) the role of Al₂O₃ as tunneling layer is highlighted.

New insight on V T stability of HK/MG stacks with scaling in 30nm FDSOI technology

In this paper it is shown that HfO2 and HfZrO oxides suffer from large VT instabilities, up to 230mV, when the device width (W) is scaled down to 80nm. It is explained by undesirable lateral oxygen diffusion through the spacers, which mainly modifies the metal workfunction in narrow transistors. HfSiO(N) oxides exhibit a much better immunity to this effect, attributed to a different crystallinity of the HK layer. Moreover, Al incorporation in the gate stack hardly changes the VT stability.

Planar Bulk + technology using TiN/Hf-based gate stack for low power applications

This work highlights the new bulk⁺ technology using high-K dielectric, single metal gate and fully depleted SON (silicon on nothing) channel for sub-45 nm low cost applications. Thin silicon channel (down to T_si= 8 nm) and thin BOX (T_box = 15 to 25 nm) are obtained using the SON process (Jurczak, 1999). Transistor performance (W_design/L_gate= 90 nm/40 nm) at V_dd = 1.1 V and I_off < 2 nA/ mum is as high as 1298 muA/ mum for nMOS and 663 muA/ mum for pMOS. In addition, reliability, noise and 6T-SRAM bit cells down to 0.249 mum² are characterized. Significant improvements with respect to conventional bulk technology are demonstrated.

Silicon-On-Nothing (SON) applications for Low Power technologies

The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices. This technology opens a wide range of applications, in particular for the realization of localized single-gate fully depleted transistors on bulk substrates and of double-gate planar devices, co-integrable with conventional bulk devices.

High-Performance High-

By introducing high-K dielectrics and metal gate in our planar self-aligned gate-all-around (GAA) fabrication process, we have successfully fabricated sub-35 nm CMOS devices that exhibit high-performance drive currents (2230/1000 muA/ mum for N/ P at Vd = 1.2 V), low off-state currents (3/5 nA/mum), and excellent subthreshold characteristics. When benchmarked with other published multigate data, the results presented in this paper are proved to be among the best and underline the potential of planar self-aligned GAA devices for the 32 nm technology and below. In particular, it is demonstrated that an optimized supply voltage can bring a significant improvement in circuit time delay and power when using GAA devices.