Charles-Alexandre Legrand

Characterization of the transient behavior of gated/STI diodes and their associated BJT in the CDM time domain

A measurement setup for the characterization of very fast transient responses in the CDM time domain is described in this paper. Experimental results are demonstrated on STI and gated diodes with a guard ring in a 65 nm and 130 nm CMOS technology. The superior behavior of gated diodes during triggering is highlighted.

Innovative ESD protections for UTBB FD-SOI technology

We present an innovative set of UTBB (Ultra-Thin Body and BOX) ESD protection devices, which achieves remarkable performance in terms of leakage current and triggering control. Ultra-low leakage current below 0.1 pA/μm and adjustable triggering (1.1V <; Vt1 <; 2.6V) capability are demonstrated. These devices rely on gate-controlled injection barriers and match the 28nm UTBB-FDSOI ESD design window by triggering before the nominal breakdown voltage of digital core MOS transistors.

A sharp-switching gateless device (Z3-FET) in advanced FDSOI technology

A systematic study of a novel band modulation device (Z3-FET: Zero gate, Zero swing slope and Zero impact ionization) fabricated in most advanced Fully Depleted Silicon-On-Insulator technology is presented. Since the device has no front gate, the operation mechanism is controlled by two buried ground planes. Characteristics such as sharp switching, low leakage, and controllable triggering are measured and discussed. We explore several variants (thin and thick silicon film) and show promising results in terms of high current and switching performance.

GDNMOS: A new high voltage device for ESD protection in 28nm UTBB FD-SOI technology

We propose a novel device (GDNMOS: Gated Diode merged NMOS) fabricated with 28nm UTBB FD-SOI high-k metal gate technology. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation, in particular in thyristor mode. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

Novel back-biased UTBB lateral SCR for FDSOI ESD protections

For the first time, a Lateral SCR (Silicon Controlled Rectifier) with Ultra-Thin Body and Buried Oxide (UTBB) is experimentally demonstrated. This device is dedicated to Electro-Static Discharge (ESD) protection and has been designed and fabricated with 28 nm Fully Depleted SOI technology. A new control technique is proposed: the use of back-gate biasing. Characteristics such as low leakage, controllable triggering (as a function of back gate voltage and ground-plane type), and device geometry are explored. We discuss several configurations (floating or locked P-base) and show promising results in terms of ESD protection performance.

Modeling a SCR-based protection structure for RF-ESD co-design simulations

Electrostatic discharge protection is a must in every integrated circuit. At microwave frequencies, the influence the protection devices have over the circuit they protect can significantly impact the functioning of the latter. A model for the SCR (silicon controlled rectifier - one of the most efficient ESD protection devices) and the ESD protection diode was developed. Its purpose is to estimate this influence at frequencies up to 65 GHz. A complex device, the DTSCR (diode triggered SCR) is used to demonstrate the consistency of the SCR and diode models.

Innovative high-density ESD protection device in state of the art UTBB FDSOI technologies

For the first time, we demonstrate an innovative way to build ESD protection in FDSOI technologies. This protection is comprised of two stacked devices one on the other: a bottom bulk-thyristor and a top thin film triggering device. Low leakage current, tunable triggering voltage and high current capability are highlighted.

Ultracompact ESD Protection With BIMOS-Merged Dual Back-to-Back SCR in Hybrid Bulk 28-nm FD-SOI Advanced CMOS Technology

The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration. It is well known that ESD protection is a challenge for IC in advanced CMOS technology. In this paper, an optimized solution is described through the concept, design, 3-D technology computer aided design (TCAD) simulation, and silicon characterization in 28-nm FD-SOI in hybrid bulk. Measurements are done thanks to transmission line pulsed (TLP), very fast TLP and dc behavior. Moreover, the overvoltage is investigated through very fast transient characterization system measurements. It demonstrates a promising candidate to protect against ESD event and to develop new ESD network dedicated to system on chip.