C. Vrancken

Systematic TLM Measurements of NiSi and PtSi Specific Contact Resistance to n- and p-Type Si in a Broad Doping Range

We present the data on specific silicide-to-silicon contact resistance (rhoc) obtained using optimized transmission-line model structures, processed for a broad range of various n- and p-type Si doping levels, with NiSi and PtSi as the silicides. These structures, despite being attractive candidates for embedding in the CMOS processes, have not been used for NiSi, which is the material of choice in modern technologies. In addition, no database for NiSi-silicon contact resistance exists, particularly for a broad range of doping levels. This letter provides such a database, using PtSi extensively studied earlier as a reference.

Silicides for the 100-nm node and beyond: Co-silicide, Co(Ni)-silicide and Ni-silicide

As scaling progresses, conventional Co/Ti silicidation is facing difficulties related to the nucleation of the low resistive Co-disilicide phase during the second RTP step of silicidation. When linewidths, junction depths and silicide thicknesses are being reduced, the RTP2 thermal process window narrows down rapidly. It is expected that the process window can be widened by alloying the Co film with Ni, because the presence of Ni lowers the nucleation barrier for the Co-disilicide phase. Replacing Co-disilicide by Ni-monosilicide is a promising alternative because the same silicide sheet resistance can be obtained with 35% less silicon consumption.

Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory

A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D NAND Flash memory is successfully developed. We introduce a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole, after which it serves as the first layer of the bilayer polysilicon channel. This approach enables the 3-D architecture to achieve minimum cell area (4F2, with F being the feature size) without the need for the so-called pipeline connections. The smallest functional cells have the memory hole diameter F = 45 nm, resulting in 22-nm channel diameter. In case 16 cells are stacked, F = 45 nm would correspond to an equivalent 11-nm planar cell technology node. Excellent program/erase and retention obtained with the all-deposited ONO stack are demonstrated.

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/low-k BEOL are some of the key features. This is an experimental demonstration of a fully working tall triple gate SRAM cell with the smallest cell size ever reported.

Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths

We demonstrate for the first time the scalability of NiSi and Ni/sub 3/Si FUSI gate processes down to 30 nm gate lengths, with linewidth independent phase and V/sub t/ control. We show that 1-step FUSI is inadequate for NiSi FUSI gates, because it results in incomplete silicidation at low thermal budgets or in a linewidth dependent Ni silicide phase - inducing V/sub t/ shifts - at higher thermal budgets. We show that V/sub t/ and WF shifts are larger on high-K (HfO/sub 2/ (250 mV) or HfSiON (330mV)) than on SiON (110mV) and report Fermi level unpinning for Ni-rich FUSI on high-K. In contrast, we demonstrate the scalability of Ni/sub 3/Si FUSI, with no phase control issues, and report HfSiON Ni/sub 3/Si FUSI PMOS devices with V/sub t/= -0.33 V. Lastly, we show that, for NiSi, phase control down to narrow gate lengths can be obtained with a 2-step FUSI process.

Comparative study of Ni-silicide and Co-silicide for sub 0.25-mm technologies

In this work, the phase formation is compared for Ni- and Co-silicidation with and without Ti cap. In addition, the electrical performance of Ni-silicidation with and without Ti-cap is investigated and compared to the performance of a Co-silicidation process with a Ti cap that has the same Si consumption. The lateral confinement of the silicide in the active areas is also studied.

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

Flexibly controllable threshold-voltage (V_th) asymmetric gate-oxide thickness (T_ox) four-terminal (4T) FinFETs with HfO₂ [equivalentoxidethickness(EOT)=1.4 nm] for the drive gate and HfO₂+thick SiO₂ (EOT=6.4-9.4 nm) for the V_th-control gate have been successfully fabricated by utilizing ion-bombardment-enhanced etching process. Owing to the slightly thick V_th-control gate oxide, the subthreshold slope (S) is significantly improved as compared to the symmetrically thin T_ox 4T-FinFETs. As a result, the asymmetric T_ox 4T-FinFETs gain higher I_on than that for the symmetrically thin T_ox 4T-FinFETs under the same I_off conditions

Hybrid Floating Gate Cell for Sub-20-nm NAND Flash Memory Technology

The hybrid floating gate (FG) concept, previously demonstrated in FG capacitors, has been proven in fully integrated stacked memory cells. Results not only confirm the high potential of the concept in terms of improved program performance, but also show excellent data retention and program/erase cycling endurance. Key for achieving this result has been the optimization of the sidewall and spacer processing. Hybrid FG cells are therefore a viable solution to extend the nand Flash memory roadmap below the 20-nm technology node.

Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?

The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures of merit. Both alternatives show better scalability than PLANAR CMOS and exhibit similar intrinsic device performance. Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced mismatch. Using an optimized integration to minimize parasitics we demonstrate high-performing FinFET ring-oscillators with delays down to 10ps/stage for both SOI and bulk FinFETs and working SRAM cells at VDD=1.0V.

Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process

Strained Ge p-channel FinFETs on Strain Relaxed SiGe are reported for the first time, demonstrating peak transconductance gmSAT of 1.3mS/μm at VDS=-0.5V and good short channel control down to 60nm gate length. Optimization of P-doping in the SiGe, optimized Si cap passivation thickness on the Ge, and improved gate wrap of the channel all improve device characteristics. The Ge FinFETs presented in this work outperform published relaxed Ge FinFET devices for the gmSAT/SSSAT benchmarking metric.