S. Biesemans

Transport Spectroscopy of a Single Dopant in a Gated Silicon Nanowire

We report on spectroscopy of a single dopant atom in silicon by resonant tunneling between source and drain of a gated nanowire etched from silicon on insulator. The electronic states of this dopant isolated in the channel appear as resonances in the low temperature conductance at energies below the conduction band edge. We observe the two possible charge states successively occupied by spin-up and spin-down electrons under magnetic field. The first resonance is consistent with the binding energy of the neutral D0 state of an arsenic donor. The second resonance shows a reduced charging energy due to the electrostatic coupling of the charged D- state with electrodes. Excited states and Zeeman splitting under magnetic field present large energies potentially useful to build atomic scale devices.

3D stacked IC demonstration using a through Silicon Via First approach

We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 0.13 mum CMOS process on 200 mm wafers. The top die is thinned down to 25 mum and bonded to the landing wafer by Cu-Cu thermo-compression. Both top and landing wafers contain CMOS finished at M2 to evaluate the process impact both FEOL and BEOL. The results confirm no degradation of the FEOL performance. The functionality of various ring oscillator topologies that include inverters distributed over both top and bottom dies connected through TSVs demonstrates excellent chip integrity after the TSV and 3D stacking process.

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single- and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.

Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO₂ based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and T_inv values of ˜5 Å and ˜8 Å respectively for both n and pMOS devices. The drive currents at I_off=100 nA/μm with V_DD=1 V is 1.4 mA/μm and 0.6 mA/μm (no SiGe source/drain) for n and pMOS respectively. The technology further offers low n/pMOS V_T of 0.3/-0.4V, good V_T-uniformity, and V_T-matching and very high cutoff frequencies at ˜290-340 GHz for 38 nm nMOS devices. A replacement poly gate process is used to further improve upon the pMOS effective work function. TDDB lifetimes over 10 years are reported while BTI indicates potential reliability challenges.

Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography

We investigate scalability, performance and variability of high aspect ratio trigate FinFETs fabricated with 193 nm immersion lithography and conventional dry etch. FinFETs with fin widths down to 5nm are achieved with record aspect ratios of 13. Excellent nMOS and pMOS performance is demonstrated for narrow fins and short gates. Further improvement in nMOS performance can be achieved by eliminating access resistance that is currently attributed to poor re-crystallization of implantation damage in narrow fins. Fully-depleted FinFETs show strongly improved short channel effect (SCE) control when the fin width is scaled, even without halo-implants. Nearly ideal DIBL and sub-threshold slope (SS) are achieved down to 30nm gate length. Low leakage devices are realized by combining a fully depleted channel, HfSiO high-k dielectric, mid-gap TiN metal electrodes, and aggressive fin width scaling. Symmetrical threshold voltages (±0.35 V) are achieved. It is demonstrated that selective epitaxial growth on source and drain regions is essential to limit parasitic resistance in narrow fin devices. Parametric spread is dominated by gate length variations in short devices but within-die fin width variations are still evident for long devices.

Review of FINFET technology

Although at single transistor and small circuits level, FINFET technology has been demonstrated to be an attractive option for advanced technology nodes, there are still important challenges to face like reduction of access resistance and the implementation of strain boosters in both NMOS and PMOS FINFET devices. The high performance sensitivity to fin dimensions (width, height, LER) sets up very tight restrictions for the process control which may create a big challenge to demonstrate process manufacturability.

3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding

In this paper we demonstrate functional 3D circuits obtained by a 3D Stacked IC approach using both Cu Through Silicon Vias (TSV) First and cost effective solution Die-to-Wafer Hybrid Collective bonding. The Cu TSV-First process is inserted between contact and M1. The top die is thinned down to 25µm and bonded to the landing wafer by Hybrid Bonding. Measurements and simulations of the power delay trade-offs of various 3D Ring Oscillator are provided as a demonstration of the relevance of such process route and of the design/simulation capabilities.

Composition influence on the physical and electrical properties of SrxTi1−xOy-based metal-insulator-metal capacitors prepared by atomic layer deposition using TiN bottom electrodes

In this work, the physical and electrical properties of SrxTi1−xOy (STO)-based metal-insulator-metal capacitors (MIMcaps) with various compositions are studied in detail. While most recent studies on STO were done on noblelike metal electrodes (Ru, Pt), this work focuses on a low temperature (250 °C) atomic layer deposition (ALD) process, using an alternative precursor set and carefully optimized processing conditions, enabling the use of low-cost, manufacturable-friendly TiN electrodes. Physical analyses show that the film crystallization temperature, its texture and morphology strongly depends on the Sr/Ti ratio. Such physical variations have a direct impact on the electric properties of SrxTi1−xOy based capacitors. It is found that Sr-enrichment result in a monotonous decrease in the dielectric constant and leakage current as predicted by ab initio calculations. The intercept of the EOT vs physical thickness plot further indicates that increasing the Sr-content at the film interface with the bottom TiN...

Layout density analysis of FinFETs

The layout of FinFETs patterned with direct lithography and spacer lithography are analysed from a circuit density perspective. Requirements on the height of the fin to obtain competitive layout density are derived. Spacer lithography will be required to obtain the layout density targets with reasonable values of fin height.

Demonstration of fully Ni-silicided metal gates on HfO/sub 2/ based high-k gate dielectrics as a candidate for low power applications

We have fabricated fully Ni-silicided metal gate (FUSI) CMOS devices with HfO2-based gate dielectrics for the first time. We demonstrate that full silicidation eliminates the Fermi level pinning at the polySi-HfO2 dielectric interface in pFETs. For nMOS devices, a 5 orders of magnitude reduction in short channel sub-threshold leakage is obtained with similar drive current compared to the poly gate devices. In addition, the FUSI process does not degrade the hysterisis nor the dielectric breakdown. This result makes FUSI on high-K a strong candidate for scaled low power technologies.