P. Absil

Work function of Ni silicide phases on HfSiON and SiO/sub 2/: NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/, and Ni/sub 3/Si fully silicided gates

A complete determination of the effective work functions (WF) of NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/ and Ni/sub 3/Si on HfSiON and on SiO/sub 2/ is presented. Conditions for formation of fully silicided (FUSI) gates for NiSi/sub 2/, NiSi, Ni/sub 3/Si/sub 2/, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/ and Ni/sub 3/Si crystalline phases were identified. A double thickness series (HfSiON/SiO/sub 2/) was used to extract WF on HfSiON accounting for charge effects. A strong effect on WF of Ni content is observed for HfSiON, with higher WF for the Ni-rich silicides suggesting unpinning of the Fermi level. A mild dependence is observed for SiO/sub 2/. While all Ni-rich silicides have adequate WF for pMOS applications, Ni/sub 2/Si is most attractive due to its low formation temperature, lower volume expansion and ease of integration. Similar threshold voltages (-0.3 V) were obtained on Ni/sub 2/Si and Ni/sub 31/Si/sub 12/ FUSI HfSiON pMOSFETS.

Layout impact on the performance of a locally strained PMOSFET

We present a study on the layout dependence of a SiGe S/D PMOSFET technology. While 65% increase in drive current is obtained for 45nm gate length transistors with large active areas, measurements and simulations show that this improvement may be seriously degraded when transistor dimensions, such as the source-drain length (L/sub s/d/) and the device width are further scaled. TDDB and NBTI measurements show that the oxide reliability is not degraded for this technology.

Performance improvement of tall triple gate devices with strained SiN layers

In this letter, we investigate the influence of tensile and compressive SiN layers on the device performance of triple-gate devices with 60-nm fin height and fin widths down to 35 nm. It will be shown that even for narrow fin devices, the nMOS performance improvement can be as high as 20% with tensile strained layers. The improvement seen for pMOS is lower, about 10%. Next to that both compressive as well as tensile SiN layers can increase the pMOS on-state current.

25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions

This paper shows, for the first time, the successful introduction of recessed, strained Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions of pMOS MuGFET devices, improving the on-state current of these devices by 25%, at a fixed off-state condition. The improvement is shown to be a combined effect of compressive stress introduced along the channel, and of a reduced series resistance.

CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:

The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni₃₁Si₁₂ FUSI gates on p-channel MOS (PMOS) with good V_t control to short gate lengths (L_G=50 nm, linear V_t of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NiSi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni₂Si or Ni₃₁Si₁₂ on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni₂Si or Ni₃₁Si₁₂ FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% I_on improvement at I_off=100 nA/mum) was obtained for Ni ₃₁Si₁₂ compared to Ni₂Si FUSI gates, as well as a V_t reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS

\hbox{Ni}_{2}\hbox{Si}

This paper demonstrates for the first time the integration of an HfO2/TiN/poly gate stack and a recessed SiGe S/D module. It also shows that by combining the SiGe stressor with a compressive nitride contact etch stop layer, it is possible to reach improvements in IDSAT of up to 65%, showing that the various strain mechanisms are additive on advanced gate stacks. This way an IDSAT of 422 muA/mum at 20pA/mum I OFF and VDD = 1.1 V can be obtained when a 25% SiGe S/D module is combined with a 1.5 GPa compressive sCESL layer

, and

In this letter, an n-type near-band edge fully silicided (FUSI) material-Yb-doped Ni FUSI is demonstrated for the first time. By doping Yb into Ni FUSI, it is shown that while maintaining the same equivalent oxide thickness and the similar device reliability, the work function of Ni FUSI (on SiON dielectrics) could be tuned from 4.72 to 4.22 eV. Yb-doped Ni FUSI is promising for the gate electrode application in n-MOSFETs.

\hbox{Ni}_{31}\hbox{Si}_{12}

The key result in this work is the experimental demonstration that adding Yb to Ni FUSI allows for tuning the work function (WF) from midgap (NiSi ~4.72 eV) to n-type band-edge (~4.22 eV) on thin SiON, maintaining same EOT. In addition, we did not observe any interface adhesion issues found in other reports when WF is modulated by dopants such as As or Sb. We also show that reliability is similar to Ni FUSI. This is a promising technique for nFET gate electrode formation and enables dual gate CMOS technologies for 45 nm and beyond in a manufacturable way

) on HfSiON

The scalability of Ni fully silicided (FUSI) gate processes to short gate lengths was studied for NiSi, Ni₂Si, and Ni₃₁Si₁₂. It is shown that the control of the deposited Ni-to-Si ratio is not effective for phase and V_t control at short gate lengths. A transition to Ni-richer phases at short gate lengths was found for nonoptimized NiSi and Ni₂Si processes with excessive thermal budgets, resulting in significant V_t shifts for devices on HfSiON consistent with the difference in work function among the Ni silicide phases. Linewidth-independent phase control with smooth V_t rolloff characteristics was demonstrated for NiSi, Ni₂Si, and Ni₃₁Si₁₂ FUSI gates by controlling the Ni-to-Si reacted ratio through optimization of the thermal budget of silicidation (prior to selective Ni removal). Phase characterization over a wide temperature range indicated that the process windows for scalable NiSi and Ni₂Si are less than or equal to 25 degC, whereas a single-phase Ni₃₁Si₁₂ is obtained over an ~200degC temperature range

Demonstration of recessed SiGe S/D and inserted metal gate on HfO/sub 2/ for high performance pFETs.

In this letter, we investigate the effects of process-induced strain on negative bias temperature instability (NBTI) by performing a comparative study of devices with and without process-induced strain for poly-Si/SiON gate stacks. Devices with SiGe source/drain with different processing sequences and devices with a combination of SiGe S/D and compressive contact etch stop layer (CESL) were studied and compared to reference devices. We decouple the effect of processing conditions in order to ensure a correct interpretation of the results. In contrast with the previous reports, which did not consider the impact of processing conditions, this letter demonstrates that, when initial threshold voltage differences are taken into account and comparisons are performed at the same oxide electric field, no significant degradation of intrinsic NBTI behavior is found for devices with a process-induced strain. In addition, we performed an Arrhenius study showing similar activation energies for devices with and without process-induced strain, suggesting similar degradation mechanism. The results indicate that process-induced strain does not create favorable conditions for additional interface state creation