C. W. Chiang

How to select adhesive materials for temporary bonding and de-bonding of 200mm and 300mm thin-wafer handling for 3D IC integration?

Handling and shipping thin wafers (≦200μm) through all the semiconductor fabrication and packaging assembly processes are very difficult since thin wafers lose the supporting strength. Usually, the thin wafer is attached to a supporting wafer with adhesive to increase its rigidity and bending stiffness. Thus, adhesive is the key enabling material for thin-wafer handling, and how to select adhesive materials for temporary bonding and de-bonding is the focus in this study. Two sizes of wafers are considered; the 200mm wafers are used to find out the important and unimportant parameters in selecting the adhesive and then apply them to the 300mm wafers. It will be shown that wafer thinning and PECVD (plasma enhanced chemical vapor deposition) in vacuum chamber are the two critical steps for thin-wafer handling. The 300mm wafers are thinned down to 50μm and evaluated in different structures including: (a) blanket wafers, (b) wafers with 80μm solder bumps, and (c) wafers with 20μm micro-bumps and TSVs in 10μm diameter and 40∼50μm pitch. Based on this study, a set of useful process guidelines and recommendations is provided.

TSV process using bottom-up Cu electroplating and its reliability test

TSV (through silicon via) is a core technology in 3D IC package. The micro vias can be made by etching or laser drilling. Standard processes for TSV filling begin with seed layer deposition, followed by blind vias copper electroplating. If the aspect ratio of the TSV is higher than 5:1, the costly MOCVD process needs to be used to deposit the seed layer with good step coverage. A special designed electroplating machine and solution for high aspect ratio copper electroplating is needed. Some researchers even use PRP (periodic reverse plating) for void free copper electroplating instead of traditional DC power supply.

3D stacked chip technology using bottom-up electroplated TSVs

In this study, bottom-up electroplating is used for TSV (Through Silicon via) fabrication. With the metal temporarily bonding technology, we could remove the handling substrate and perform the chip stacking process. The TSVs made by bottom-up electroplating do not need the expensive MOCVD seed layer deposition and special designed electroplater/solution. Moreover, it is independent with the DRIE angle and the scallop at the sidewall of the vias. By using the bottom-up electroplating technology, we could fabricate the TSVs in much shorter process time to save the process cost. From the X-Ray images and the SEM pictures, the diameter of the vias is 5.3 micron meters and the length of the vias is 67 micron meters. The aspect ratio of the bottom-up electroplated TSVs is larger than 12 and all the vias are definitely void free. X-Ray image also shows the process yield is very high. After the thermal shock reliability test, the resistance measurement and the vias are fine from the SEM pictures. There is no crack found at the sidewall of the vias. After the TSV process, the bonded electrode continues to serve as electrode for the mask-less Sn electroplating. The electroplating current goes through the bottom electrode TSVs and the Sn is electroplated on the TSVs without mask define. Sn bump served as mechanical and electrical connection. We also demonstrate the dry etching process for wafer thinning on a 170°C thermal release tape with handling substrate. After the etching process, the thickness of the chip is about 5µm and then it is released from the handling substrate successfully. For thin wafer handling technology, we proposed a metal temporarily bonding technology. Au to Au bonding is used here for metal temporarily bonding. After the wafer thinning process, the sample could sustain high temperature process without crack and could be removed from the handling substrate after the process. This study also demonstrates the process flow for the 3D chip stacking by using the bottom-up electroplated TSVs. The handling substrate is removed by metal temporarily bonding technology and the interconnection is done by Cu/Sn bump. Based on this technology, the TSVs in the 3D chip stacking could be made in shorter electroplating time and low cost way by a traditional electroplater.

Low temperature process evaluation for 3DIC integrated thin wafer handling

The goal of temporary wafer bonding for 3DIC thin wafer handling is less topographic issues and high temperature resistance. The wafer thinning and process in vacuum chamber with high temperature are the key for the 3DIC thin wafer handling. In this article a quick adhesive selecting methods, and process improvement results are evaluated and discussed.

Process integration of backside illuminated image sensor with thin wafer handling technology

In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of CMOS image sensor is temporarily bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to few microns to detect the light from the backside. After thinning process, the backside is permanently bonded to a glass carrier substrate with a transparent thermal set bonding material. By using a special trim from glass step, the temporarily bonded silicon carrier could be removed. Cu/Sn micro-bump is then fabricated at the front-side of the CMOS image sensor. No TSVs are needed in the proposed structure. A 300 mm silicon wafer with micro bumps bonded on 500 μm-thick glass wafer is demonstrated. Void free bonding is obtained by IR inspection both in temporary bonding and permanent bonding processes. The thickness of the silicon wafer is measured by IR system and the average thickness of the silicon wafer is 6.4 μm. After thinning, 1 μm TTV is obtained because the thermal plastic material flow during bonding process resulted in excellent planarization. From the cross sectional SEM image, Cu/Sn micro bump with thickness 4 μm/5 μm is formed at the front-side of the CMOS image sensor. The run-out issues from CTE mismatch is also discussed in this study.

Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding

In this study, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding is demonstrated. To realize the signal transmission effects in high speed digital signaling via Cu TSV and Cu/Sn micro-joint interconnection, the insertion loss was investigated by simulation analysis with variable TSV pitches, micro-bump diameters and chip thicknesses. Key technologies include TSV fabrication, micro-bumping, hybrid scheme making, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. 5μm TSV, 10μm micro-bump, 20μm pitch, 40μm thin wafer, and 250°C low temperature W2W hybrid bonding have been successfully integrated in the integration platform. The 3D scheme was characterized and assessed to have excellent electrical performance and reliability, and is potentially to be applied for 3D product applications.

TSV-less BSI-CIS wafer-level package and stacked CIS module

In this study, a back-side illuminated CMOS image sensor (BSI-CIS) without through-silicon via (TSV) is developed with thin wafer handling combination with ultra-wafer thinning technologies. The CIS wafer is implemented front-side processes then temporarily bonded on a Si carrier by Brewer Science adhesive with ZoneBOND™ technology applied. The ZoneBOND™ technology provides a promising solution for thin wafer handling with temporary bonding, wafer thinning, thin wafer processes, and de-bonding. After thinning, the CIS backside is bonded with glass wafer, and the Si carrier is removed using solvent dipping for de-bonding. The thickness of BSI-CIS without TSV is less than 5μm, which is visible light transparent to meet the back-side illumination requirement. Cu/Sn bumps with 50μm size are formed with the bump height uniformity less than 5% in wafer level. The completed BSI-CIS is then assembled on Si substrate. There are totally 400 bumps in this test vehicle design. The Cu/Ni/Au UBMs on Si substrate bonded with Cu/Sn bumps on CIS is conducted by thermal compression bonding. The wafer-level package of TSV-less BSI-CIS has been successfully developed and demonstrated, stacked module is accomplished and passed 1000 cycles of -55°C~125°C TCT in the paper.

Thin wafer handling process evaluation for 3DIC integration

After temporary bonding and thinning process, many backside processes will be conducted on the thinned wafer. The critical processes for thin wafer handling material are high temperature and high vacuum processes. In this article, a quick adhesive selecting method is proposed. Backside process of PECVD SiO2 is identified as the most critical process for thin wafer handling material selection. Two thermal plastic thin wafer handling materials are used in this study for 300 mm wafers and thermal compress bonding in a vacuum chamber is used for bonding process. After bonding, the wafer is thinned down to 50 μm by a commercialized grinder and the PECVD SiO2 process is conducted on the thinned wafer. Many dishes were found after PECVD SiO2 process because there is outgassing from the thin wafer handling material or from the device/carrier wafer surface. In this research, an additional hold time is proposed to reduce the dishing after PECVD SiO2 process. Different hold time at 210 °C and different bonding time are evaluated. For the bonding process without hold time, large voids are observed. There are also 29 dishes on the surface of the wafer. By adding additional 5 minutes hold time before bonding, the number of the dishing on the wafer surface reduced from 29 to 6. If the hold time is set to 10 minutes, only 4 dishes were found on the wafer surface. From the evaluation result of these two thermal plastic thin wafer handling materials, B-glue seems much better than A-glue. The hold time seems very critical on void reduction during bonding process. From B-glue on PECVD SiO2 experiment, 10 minutes hold time has the better performance for void reduction. The bonding process with zero hold time has the worst performance which has many voids after PECVD SiO2 process. An ultra-thin 300 mm wafer with a thickness less than 7 μm is also demonstrated in this research by using B-glue and 10 minutes hold time.