Hsiang-Hung Chang

How to select adhesive materials for temporary bonding and de-bonding of 200mm and 300mm thin-wafer handling for 3D IC integration?

Handling and shipping thin wafers (≦200μm) through all the semiconductor fabrication and packaging assembly processes are very difficult since thin wafers lose the supporting strength. Usually, the thin wafer is attached to a supporting wafer with adhesive to increase its rigidity and bending stiffness. Thus, adhesive is the key enabling material for thin-wafer handling, and how to select adhesive materials for temporary bonding and de-bonding is the focus in this study. Two sizes of wafers are considered; the 200mm wafers are used to find out the important and unimportant parameters in selecting the adhesive and then apply them to the 300mm wafers. It will be shown that wafer thinning and PECVD (plasma enhanced chemical vapor deposition) in vacuum chamber are the two critical steps for thin-wafer handling. The 300mm wafers are thinned down to 50μm and evaluated in different structures including: (a) blanket wafers, (b) wafers with 80μm solder bumps, and (c) wafers with 20μm micro-bumps and TSVs in 10μm diameter and 40∼50μm pitch. Based on this study, a set of useful process guidelines and recommendations is provided.

3D stacked chip technology using bottom-up electroplated TSVs

In this study, bottom-up electroplating is used for TSV (Through Silicon via) fabrication. With the metal temporarily bonding technology, we could remove the handling substrate and perform the chip stacking process. The TSVs made by bottom-up electroplating do not need the expensive MOCVD seed layer deposition and special designed electroplater/solution. Moreover, it is independent with the DRIE angle and the scallop at the sidewall of the vias. By using the bottom-up electroplating technology, we could fabricate the TSVs in much shorter process time to save the process cost. From the X-Ray images and the SEM pictures, the diameter of the vias is 5.3 micron meters and the length of the vias is 67 micron meters. The aspect ratio of the bottom-up electroplated TSVs is larger than 12 and all the vias are definitely void free. X-Ray image also shows the process yield is very high. After the thermal shock reliability test, the resistance measurement and the vias are fine from the SEM pictures. There is no crack found at the sidewall of the vias. After the TSV process, the bonded electrode continues to serve as electrode for the mask-less Sn electroplating. The electroplating current goes through the bottom electrode TSVs and the Sn is electroplated on the TSVs without mask define. Sn bump served as mechanical and electrical connection. We also demonstrate the dry etching process for wafer thinning on a 170°C thermal release tape with handling substrate. After the etching process, the thickness of the chip is about 5µm and then it is released from the handling substrate successfully. For thin wafer handling technology, we proposed a metal temporarily bonding technology. Au to Au bonding is used here for metal temporarily bonding. After the wafer thinning process, the sample could sustain high temperature process without crack and could be removed from the handling substrate after the process. This study also demonstrates the process flow for the 3D chip stacking by using the bottom-up electroplated TSVs. The handling substrate is removed by metal temporarily bonding technology and the interconnection is done by Cu/Sn bump. Based on this technology, the TSVs in the 3D chip stacking could be made in shorter electroplating time and low cost way by a traditional electroplater.

Process, assembly and electromigration characteristics of glass interposer for 3D integration

Glass interposer is proposed as a superior alternative to organic and silicon-based interposers for 3DIC packaging in the near future. Because glass is an excellent dielectric material and could be fabricated with large size, it provides several attractive advantages such as excellent electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In this paper, we investigated the EM performance of Cu RDL line with glass substrate. Three different physical properties of glass materials were used for studying the EM performance of Cu RDL line. The used testing conditions are under 150~170 °C and 300~500mA. The glass type material with best performance was applied for glass interposer process integration and assembly investigation. Therefore, a wafer-level 300mm glass interposer scheme with topside RDLs, Cu TGVs, bottom side RDLs, Cu/Sn micro-bump and PBO passivation has been successfully developed and demonstrated in the study. The chip stack modules with glass interposer were assembled to evaluate their electrical characteristics. Pre-conditioning test was performed on the chip stacking module with the glass interposer to assess the reliability of the heterogeneous 3D integration scheme. All the results indicate that the glass interposer with polymer passivation can be successfully integrated with lower cost processes and assembly has been successfully developed and demonstrated in the study.

Performance and process characteristic of glass interposer with through-glass-via(TGV)

Primary approach of 3DIC packaging usually adopts organic substrates or silicon interposer as the intermedium between multi-integrated circuits (ICs) and printed circuit board. Current organic substrates face the limitations in poor dimensional stability, trace density and CTE mismatch to silicon. Silicon interposer is a good solution for high-pin-count ICs and high performance applications based on the mature Si technology of advance via formation and fine line Cu damascene multilevel interconnection process, but silicon interposer is limited by high cost. Glass is proposed as ideal interposer material due to high resistivity, low dielectric constant, low insertion loss and adjustable coefficient of thermal expansion (CTE) for the 3DIC assembly integration and most importantly low cost solution, [1-4]. The main focus of this paper is on (a) TGV electrical design, simulation and characterization, (b) wafer level integration in TGV formation, two RDL on the front-side, one RDL on the backside and polymer-based PBO for the passivation, (c) assembly process of silicon chip stack on the glass interposer with Kelvin resistance measurement. The glass interposer was assessed to have excellent electrical characteristics and is potentially to be applied for 3D product applications.

Process integration and reliability test for 3D chip stacking with thin wafer handling technology

In this study, a three-dimensional (3D) integrated circuit (IC) chip stacking structure with a through-silicon via (TSV) is proposed. A high aspect ratio, void-free Cu electro-plating technology was achieved through super filling. The aspect ratio of the TSV was larger than eight. For chip stacking, Cu/Sn micro bumps with diameters less than 20 μm were used. Solder shape prediction using surface evolver showed good correlation with experiment results within a 2.5% error. Thin wafer handling technology with thermal plastic material was also adopted in this paper. The outgassing issue for silicon dioxide (SiO2) was improved dramatically when an additional silicon nitride (Si3N4) film deposition was made. Using the slide-off method with thermal plastic thin wafer handling material, an eight-inch wafer with a thickness of less than 50 μm was processed. After the die-saw process, ten chips could be stacked using the die bonder. Thermal cycling reliability test was also conducted with the temperature ranging from −55 to 125 ºC. The reliability life for the proposed structure was 3,777 cycles from the Weibull plot. The average resistance for one interconnection was less than 50 mΩ. A 3D finite element model was also established in this study. The CTE mismatch between the polyimide and the silicon resulted in warpage. The simulation results showed that the maximum von Mises stress occurred at the corner of the TSV which could lead to a failure mode called “copper pumping.” For the von Mises stress in the micro bump, the maximum value occurred between the inter-metallic compound and the substrate copper pad. From the cross-sectional SEM image of the failed sample after thermal cycling test, the failure mode had good correlation with the simulation results. Equivalent plastic strain was around 0.11% in this simulation. As both silicon substrate and silicon chips were used in this study, a small equivalent plastic strain is expected.

Process integration of 3D Si interposer with double-sided active chip attachments

A double-sided Si passive interposer connecting active dies on both sides for a 3D IC integration is investigated. This interposer is 100μm-thick with 10μm-diameter TSVs (through silicon vias), 3 RDLs (redistribution layer) on its front-side, 2 RDLs on its backside. It supports 2 active dies on its frontside and 1 active die at its backside. The present study focuses on the process integration of the passive interposer, double-sided chip assembly process, and passive electrical characterization.

3D Chip-to-Chip Stacking with Through Silicon Interconnects

The paper describes the newly development technology of 3D stacking packaging by introducing laser-drilled through silicon interconnect (LTSI). Compared to the recently abundant researches of 3D chip-to-wafer or wafer-to-wafer stacking, it demonstrated a more reliable and practical process flow to achieve the 3D stacking technology. The investigation of thermal effect and electrical properties on LTSI confirm that this newly low-cost interconnect technology could be a good candidate for both wafer stacking application and 3D SiP module.

Flexible Electronic-Optical Local Bus Modules to the Board-to-Board, Board-to-Chip, and Chip-to-Chip Optical Interconnection

In this paper, a flexible active E/O local bus module using multi-mode optical transmission is proposed to perform board-to-board, chip-to-chip, or board-to-chip optical interconnection with compatibility to traditionally electrical interfaces. In this proposed scheme, high speed modules or chips on tradition printed circuit board (PCB) can be directly interconnected through a flexible active E/O cable which can actively convert high speed signals to/from optical forms and then transmit optical signals through the optical waveguide layer. A 17-cm long prototyping of the proposed E/O local bus module is developed here to demonstrate the feasibility of short reach optical interconnection in board level applications

A Novel 3D Integration Scheme for Backside Illuminated CMOS Image Sensor Devices

A novel backside-illuminated CMOS image sensor (BSI-CIS) scheme and process are developed and demonstrated. This innovative scheme can be realized without fusion oxide bonding and through-silicon via (TSV) fabrication. This wafer-level TSV-less BSI-CIS scheme includes transparent ultrathin silicon (~ 3.6 μm) and uses several bonding technologies. The characterization and assessment results indicate that the integration scheme possesses excellent electrical integrity and reliability. In addition, good quality results of the image functional test demonstrate the excellent performance of this scheme. This novel scheme also provides a realizable low-cost solution for the next-generation CIS and further 3-D novel BSI-CIS scheme.

Process integration of backside illuminated image sensor with thin wafer handling technology

In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of CMOS image sensor is temporarily bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to few microns to detect the light from the backside. After thinning process, the backside is permanently bonded to a glass carrier substrate with a transparent thermal set bonding material. By using a special trim from glass step, the temporarily bonded silicon carrier could be removed. Cu/Sn micro-bump is then fabricated at the front-side of the CMOS image sensor. No TSVs are needed in the proposed structure. A 300 mm silicon wafer with micro bumps bonded on 500 μm-thick glass wafer is demonstrated. Void free bonding is obtained by IR inspection both in temporary bonding and permanent bonding processes. The thickness of the silicon wafer is measured by IR system and the average thickness of the silicon wafer is 6.4 μm. After thinning, 1 μm TTV is obtained because the thermal plastic material flow during bonding process resulted in excellent planarization. From the cross sectional SEM image, Cu/Sn micro bump with thickness 4 μm/5 μm is formed at the front-side of the CMOS image sensor. The run-out issues from CTE mismatch is also discussed in this study.