Huan-Chun Fu

How to select adhesive materials for temporary bonding and de-bonding of 200mm and 300mm thin-wafer handling for 3D IC integration?

Handling and shipping thin wafers (≦200μm) through all the semiconductor fabrication and packaging assembly processes are very difficult since thin wafers lose the supporting strength. Usually, the thin wafer is attached to a supporting wafer with adhesive to increase its rigidity and bending stiffness. Thus, adhesive is the key enabling material for thin-wafer handling, and how to select adhesive materials for temporary bonding and de-bonding is the focus in this study. Two sizes of wafers are considered; the 200mm wafers are used to find out the important and unimportant parameters in selecting the adhesive and then apply them to the 300mm wafers. It will be shown that wafer thinning and PECVD (plasma enhanced chemical vapor deposition) in vacuum chamber are the two critical steps for thin-wafer handling. The 300mm wafers are thinned down to 50μm and evaluated in different structures including: (a) blanket wafers, (b) wafers with 80μm solder bumps, and (c) wafers with 20μm micro-bumps and TSVs in 10μm diameter and 40∼50μm pitch. Based on this study, a set of useful process guidelines and recommendations is provided.

Characterization and reliability assessment of solder microbumps and assembly for 3D IC integration

In this investigation, Cu/Sn lead-free solder microbumps with 10μm pads on 20μm pitch are designed and fabricated. The chip size is 5mm × 5mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability Assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but still achieve good plating uniformity. With the current process, the undercut is less than 1μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder micro bumped chip is bonded on a Si wafer (chip-to-wafer or C2W bonding). Furthermore, the micro-gap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips w/o underfill is measured and exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, SAT analysis, and cross-section with SEM analysis. The stacked ICs are evaluated by reliability tests, including thermal cycling test (−55⇆125°C, dwell and ramp times = 15 min). Finally, ultra find-pitch (5μm pads on 10μm pitch) lead-free solder microbumping is explored.

Wafer Bumping, Assembly, and Reliability of Fine-Pitch Lead-Free Micro Solder Joints for 3-D IC Integration

In this investigation, Cu-Sn lead-free solder microbumps on 10-μm pads with a 20-μm pitch are designed and fabricated. The chip size is 5 × 5 mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but to still achieve good plating uniformity. With the current process, the undercut is less than 1 μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder microbumped chip is bonded on an Si wafer using chip-to-wafer bonding technique. Furthermore, the microgap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips without the underfill is measured and it exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, scanning acoustic tomography analysis, and cross-section with scanning electron microscopy analysis. The stacked ICs are evaluated by reliability (thermal cycling) test (-55 to 125°C). Finally, ultrafine-pitch (5-μm pads on a 10-μm pitch) lead-free solder microbumping is explored.

Wafer-level 3D integration using hybrid bonding

In this paper, several material candidates for hybrid bonding technology in wafer-level 3D integration were investigated. Polymer materials, including BCB, SU-8, AL-Polymer, and polyimide (PI), were studied and then thermal-compression bonded between 150°C and 450°C. Characterization of bonded layer and evaluation of bond quality for these bonded wafers were investigated by Scanning Acoustic Tomograph (SAT), dicing test, shear test, and cross-sectional SEM. To understand the behavior and physics meaning of failure bonding, the mechanism is studied to explain the relation between bonding failure and material properties. In addition, samples with hybrid scheme were fabricated to perform hybrid bonding and realize the compatibility in whole processes. The demonstration of wafer-level 3D integration using hybrid bonding is significant to prove the manufacturability of 3D IC applications.

Process, assembly and electromigration characteristics of glass interposer for 3D integration

Glass interposer is proposed as a superior alternative to organic and silicon-based interposers for 3DIC packaging in the near future. Because glass is an excellent dielectric material and could be fabricated with large size, it provides several attractive advantages such as excellent electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In this paper, we investigated the EM performance of Cu RDL line with glass substrate. Three different physical properties of glass materials were used for studying the EM performance of Cu RDL line. The used testing conditions are under 150~170 °C and 300~500mA. The glass type material with best performance was applied for glass interposer process integration and assembly investigation. Therefore, a wafer-level 300mm glass interposer scheme with topside RDLs, Cu TGVs, bottom side RDLs, Cu/Sn micro-bump and PBO passivation has been successfully developed and demonstrated in the study. The chip stack modules with glass interposer were assembled to evaluate their electrical characteristics. Pre-conditioning test was performed on the chip stacking module with the glass interposer to assess the reliability of the heterogeneous 3D integration scheme. All the results indicate that the glass interposer with polymer passivation can be successfully integrated with lower cost processes and assembly has been successfully developed and demonstrated in the study.

A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application

Thin wafer/chip stacking with vertical interconnect by a Cu through-silicon via (TSV) and a Cu/Sn microjoint is one of the candidates for 3-D integration. The insertion loss of the two-chip stack was evaluated with different TSV pitches, microbump diameters, and chip thicknesses to realize the signal transmission effects in high-speed digital signaling via TSV and microjoint interconnection. In addition, a wafer-level 3-D integration scheme with Cu TSVs based on Cu/Sn microbump and BCB adhesive hybrid bonding was demonstrated. Key technologies, including TSV interconnection, microbumping, hybrid bonding, wafer thinning, and backside RDL formation, were well developed and integrated to realize 3-D integration. This paper presents a complete study of the structure design, the process condition, and the electrical and reliability assessment of the wafer-level 3-D integration scheme. This 3-D integration scheme with excellent electrical performance and reliability provides a promising solution for 3-D memory application.

Performance and process characteristic of glass interposer with through-glass-via(TGV)

Primary approach of 3DIC packaging usually adopts organic substrates or silicon interposer as the intermedium between multi-integrated circuits (ICs) and printed circuit board. Current organic substrates face the limitations in poor dimensional stability, trace density and CTE mismatch to silicon. Silicon interposer is a good solution for high-pin-count ICs and high performance applications based on the mature Si technology of advance via formation and fine line Cu damascene multilevel interconnection process, but silicon interposer is limited by high cost. Glass is proposed as ideal interposer material due to high resistivity, low dielectric constant, low insertion loss and adjustable coefficient of thermal expansion (CTE) for the 3DIC assembly integration and most importantly low cost solution, [1-4]. The main focus of this paper is on (a) TGV electrical design, simulation and characterization, (b) wafer level integration in TGV formation, two RDL on the front-side, one RDL on the backside and polymer-based PBO for the passivation, (c) assembly process of silicon chip stack on the glass interposer with Kelvin resistance measurement. The glass interposer was assessed to have excellent electrical characteristics and is potentially to be applied for 3D product applications.

Process integration and reliability test for 3D chip stacking with thin wafer handling technology

In this study, a three-dimensional (3D) integrated circuit (IC) chip stacking structure with a through-silicon via (TSV) is proposed. A high aspect ratio, void-free Cu electro-plating technology was achieved through super filling. The aspect ratio of the TSV was larger than eight. For chip stacking, Cu/Sn micro bumps with diameters less than 20 μm were used. Solder shape prediction using surface evolver showed good correlation with experiment results within a 2.5% error. Thin wafer handling technology with thermal plastic material was also adopted in this paper. The outgassing issue for silicon dioxide (SiO2) was improved dramatically when an additional silicon nitride (Si3N4) film deposition was made. Using the slide-off method with thermal plastic thin wafer handling material, an eight-inch wafer with a thickness of less than 50 μm was processed. After the die-saw process, ten chips could be stacked using the die bonder. Thermal cycling reliability test was also conducted with the temperature ranging from −55 to 125 ºC. The reliability life for the proposed structure was 3,777 cycles from the Weibull plot. The average resistance for one interconnection was less than 50 mΩ. A 3D finite element model was also established in this study. The CTE mismatch between the polyimide and the silicon resulted in warpage. The simulation results showed that the maximum von Mises stress occurred at the corner of the TSV which could lead to a failure mode called “copper pumping.” For the von Mises stress in the micro bump, the maximum value occurred between the inter-metallic compound and the substrate copper pad. From the cross-sectional SEM image of the failed sample after thermal cycling test, the failure mode had good correlation with the simulation results. Equivalent plastic strain was around 0.11% in this simulation. As both silicon substrate and silicon chips were used in this study, a small equivalent plastic strain is expected.

Wafer-to-wafer hybrid bonding technology for 3D IC

In this research, the wafer-level metal/adhesive hybrid bonding technology was developed to perform the 3D integration platform. Four kinds of polymer materials, BCB, SU-8, AL-Polymer, and PI, were evaluated as the bonding adhesive for hybrid collocation with metal. After realizing the bonding properties, the qualified ones were patterned on wafers, and sequentially bonded by metal bonding conditions. Two kinds of conditions were simulated, one is Cu-Sn eutectic bonding, and the other is Cu-Cu thermo-compression bonding. The compatibility between each polymer and metal was evaluated, and the application range of each material was established thereof. Furthermore, samples with hybrid scheme were fabricated to perform hybrid bonding and realize the compatibility in whole process. The micro-bump/Cu-pad size less than 20µm and thickness less than 5µm were designed for interconnection. The bonding quality and interface investigation on metal/adhesive were analyzed to make sure the interconnection and micro-gap filling between stacked wafers. The evaluation results of wafer-level hybrid bonding and material candidates will be disclosed in the paper.

Investigation of the process for glass interposer

Through glass via (TGV) interposer fabrication processes are critical techniques in 3D-IC integration, providing the short interconnection among different stacked chips and substrate. Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, flexibility with CTE and most importantly low cost solution. In this investigation, the glass interposer by using TSV industry equipment and tooling was evaluated and developed and there are many challenges for processing. For process, the major differences between Glass and Si interposer are method for via formation and isolation. The test vehicle for Glass interposer is successfully processed. Glass material is composed with SiOx, it is good isolation for electrical current. The polymer-based PBO is used for passivation. For structure of glass interposer, there is one RDL on the front-side and backside, respectively. The other structure is 2 RDL on the front-side and one RDL one the backside. The CD of through glass via is 30 μm, it is formed by Corning Co. Cu overburden and Ti barrier are removed by wet etching process. For top RDL (line-width = 20μm), Cu plating process with seed layer (Ti/Cu) wet-etching process is applied. The PBO material is used for passivation, the process temperature is blow 200°C. Top UBM (15μm in diameter; 4μm/5μm-thick Cu/Sn) is formed with a top passivation opening (15μm). The structure is analyzed and demonstrated by SEM analysis. All the results indicate that the glass interposer with polymer passivation can be preceded and the cost for process is cheaper than Si interposer.