Calvin King

A 3D-IC Technology with Integrated Microchannel Cooling

A 3D-IC technology with integrated microchannel cooling is demonstrated in this paper. Fluidic interconnect network fabrication proceeds at the wafer-level, is compatible with CMOS processing and flip-chip assembly and requires four lithography steps. Measurements for single chips prior to 3D stacking reveal that each die in a two chip 3D stack may potentially exhibit a junction-to-ambient thermal resistance of 0.24°C/W. The demonstrated silicon die contain a through-silicon copper via density of 2500/cm2 integrated within the microchannel heat sink.

3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation

This paper describes a novel 3D integration technology that enables the integration of electrical, optical, and microfluidic interconnects in a 3D die stack. The electrical interconnects are used to provide power delivery and signaling, the optical interconnects are used to enable optical signal routing to all levels of the 3D stack, and the microfluidic interconnects are used to cool each level in the 3D stack and thus enable stacking of high-performance (high-power) dice. These interconnects are integrated in a 3D stack both as through-silicon vias (TSVs) and as input/output (I/O) interconnects. Design trade-offs (TSV density, power supply noise, thermal resistance, and pump size), fabrication, and assembly are reported.

Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips

Power dissipation in microprocessors is projected to reach a level that may necessitate chip-level liquid cooling in the near future. An on-chip microchannel heat sink can reduce the total thermal interfaces between an integrated circuit chip and the convective cooling medium and therefore yield smaller junction-to-ambient thermal resistance. This paper reports the fabrication, assembly, and testing of a silicon chip with complementary metal-oxide-semiconductor process compatible microchannel heat sink and thermofluidic chip input/output (I/O) interconnects fabricated using wafer-level batch processing. Ultra-small form factor, low-cost fabrication and assembly (system integration) are achieved for 2D and 3D chips, as the microchannel heat sink is fabricated directly on back-side of each chip. Through-wafer electrical and fluidic vias are used to interconnect the monolithically integrated microchannel heat sink to thermofluidic chip I/O interconnections. The feasibility of the novel fluidic I/O interconnect is demonstrated through preliminary thermal resistance measurements.

3D stacking of chips with electrical and microfluidic I/O interconnects

Motivations for three-dimensional (3D) integration include reduction in system size, interconnect delay, power dissipation and enabling hyper-integration of chips fabricated using disparate process technologies. Although various low-power commercial products exploit the advantages of improved performance and increased device packing density realized by 3D stacking of chips (using wirebonds), such technologies are not suitable for high-performance chips due to ineffective power delivery and heat removal. This is important because high performance chips are projected to dissipate more than 100 W/cm2 and require more than 100 A of supply current. Consequently, when such chips are stacked, the challenges in power delivery and cooling become greatly exacerbated. Thus, revolutionary interconnection and packaging technologies will be needed to address these limits [Bakir, et. al., (2007)]. This paper reports, for the first time, the configuration, fabrication, and experimental results of a 3D integration platform that can support the power delivery, signaling, and heat removal requirements for high-performance chips. The key behind this 3D platform is the ability to process integrate, at the wafer-level, electrical and microfluidic interconnection networks on the wafer containing the electrical circuitry and assemble such chips using conventional flip-chip technology.

Electrical and fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs

Heat removal technologies are among the most critical needs for 3D integration of high-performance microprocessors. As high performance chips are projected to dissipate more than 100W/cm2 and require more than 100A of supply current, integrating high performance chips in a 3D stack greatly exacerbates challenges in power delivery and cooling of chips within the stack. This paper reports the configuration of a 3D integration platform that can support the power delivery, signaling, and heat removal requirements for 3D architectures with integrated high-performance processors in the 3D stack. The researchers demonstrate the use of wafer-level batch fabrication to develop advanced electrical and fluidic three-dimensional interconnect networks in a 3D stack. The on-chip integrated microchannel heat sinks enable cooling of >100W/cm2 of each high power density chip. A key element in this platform is the ability to assemble chips with electrical and fluidic I/Os and seal fluidic interconnections at each strata interface. Three assembly and fluidic sealing techniques are discussed. Fabrication, assembly, and experimental results of the novel fluidic sealing technologies that enable the microfluidic network in the inter-layer liquid cooling 3D integration platform are also reported.

Revolutionary Innovation in System Interconnection: A New Era for the IC

This paper describes novel microscale electrical, optical, and fluidic interconnect networks to address off-chip interconnect challenges in high-performance computing systems as well as to enable 3D heterogeneous integration of CMOS and MEMS/sensors.

Electrical, optical, and fluidic interconnect networks for 3D heterogeneous integrated systems

Three-dimensional (3D) system integration is widely accepted as a key enabler for future systems. Although there are a number of approaches to 3D integration, none have addressed the need for cooling in a 3D stack of high-performance chips (microprocessors). This is a significant omission and imposes a constraint on the ability to fully utilize the benefits of 3D technology. Thus, new 3D integration technologies are needed for high-performance applications as well as those that require the integration of photonics within the 3D stack.