Camille Petit-Etienne

Reducing damage to Si substrates during gate etching processes by synchronous plasma pulsing

Plasma oxidation of the c-Si substrate through a very thin gate oxide layer can be observed during HBr/O2/Ar based plasma overetch steps of gate etch processes. This phenomenon generates the so-called silicon recess in the channel and source/drain regions of the transistors. In this work, the authors compare the silicon recess generated by continuous wave HBr/O2/Ar plasmas and synchronous pulsed HBr/O2/Ar plasmas. Thin SiO2 layers are exposed to continuous and pulsed HBr/O2/Ar plasmas, reproducing the overetch process conditions of a typical gate etch process. Using in situ ellipsometry and angle resolved X-ray photoelectron spectroscopy, the authors demonstrate that the oxidized layer which leads to silicon recess can be reduced from 4 to 0.8 nm by pulsing the plasma in synchronous mode.

Silicon recess minimization during gate patterning using synchronous plasma pulsing

With the emergence of new semiconductor devices and architectures, there is a real need to limit plasma induced damage. This study clearly demonstrates the capability of pulsed plasma technology to minimize plasma induced silicon oxidation that leads to the silicon recess phenomenon during polysilicon gate patterning. Indeed, the authors show that by pulsing optimized continuous wave overetch plasma conditions using HBr/He/O2 plasmas, the silicon recess is reduced from 0.6 to 0.2 nm, while the gate profiles are maintained anisotropic. Synchronous pulsed plasmas open new paths to pattern complex stacks of ultrathin materials without surface damage.

Etching mechanisms of thin SiO2 exposed to Cl2 plasma

Plasma etching is the most standard patterning technology used in micro- and nano-technologies. Chlorine-based plasmas are often used for silicon etching. However, the behavior of thin silicon oxide exposed to such a plasma is still not fully understood. In this paper, we investigate how a thin silicon oxide layer on silicon behaves when it is exposed to a Cl2 plasma. The authors show that chlorine atoms diffuse and/or Cl+ ions are implanted through the thin (<2.5 nm) oxide, leading to the formation of a SiClx interface layer between the two layers of Si and SiO2. Chlorine accumulates at the interface until the SiO2 is thin enough to release volatile SiClx species and the silicon begins to be etched.

Atomic-scale silicon etching control using pulsed Cl2 plasma

Plasma etching has been a key driver of miniaturization technologies toward smaller and more powerful devices in the semiconductor industry. Thin layers involved in complex stacks of materials are approaching the atomic level. Furthermore, new categories of devices have complex architectures, leading to new challenges in terms of plasma etching. New plasma processes that are capable to etch ultra-thin layers of materials with control at the atomic level are now required. In this paper, the authors demonstrate that Si etching in Cl2 plasma using plasma pulsing is a promising way to decrease the plasma-induced damage of materials. A controlled etch rate of 0.2 nm min−1 is reported by pulsing the chlorine plasma at very low duty cycles. Using quasi-in-situ angle resolved XPS analyses, they show that the surface of crystalline silicon is less chlorinated, the amorphization of the top crystalline silicon surface is decreased, and the chamber wall are less sputtered in pulsed plasmas compared to continuous wave plasmas. This is attributed to the lower density of radicals, lower ion flux, and lower V-UV flux when the plasma is pulsed.

Towards new plasma technologies for 22nm gate etch processes and beyond

Since more than 30 years, CW plasmas have been used in the microelectronics industry to pattern complex stacks of materials involved in Integrated Circuit technologies. Even if miniaturization challenges have been successfully addressed thanks to plasma patterning technologies, several fundamental limitations of the plasmas remain and are limiting our ability to shrink further the device dimensions. In this work, we analyze the capabilities of synchronized pulsed ICP technologies and their potential benefits for front end etch process performance. The impact of duty cycle and frequency on the ion energy distribution function and plasma chemistry is analyzed. Our results show that decreasing the duty cycle in ICP plasmas generates less fragmentation of the feed gas stock molecules compared to CW plasmas, leading in final to a decrease of the radical density in the plasma. On a process point of view, we have studied the etching of ultra-thin layers (SiO2, HfO2,SiN spacer) involved in front end processes and investigated what synchronized pulsed plasmas could bring to substrate damage and selectivity issues.

Optimization of H2 thermal annealing process for the fabrication of ultra-low loss sub-micron silicon-on-insulator rib waveguides

The superior confinement of light provided by the high refractive index contrast in Si/SiO2 waveguides allows the use of sub-micron photonic waveguides. However, when downscaling waveguides to sub-micron dimensions, propagation losses become dominated by sidewall roughness scattering. In a previous study, we have shown that hydrogen annealing after waveguide patterning yielded smooth silicon sidewalls. Our optimized silicon patterning process flow allowed us to reduce the sidewall roughness down to 0.25 nm (1σ) while maintaining rectangular Strip waveguides. As a result, record low optical losses of less than 1 dB/cm were measured at telecom wavelengths for waveguides with dimensions larger than 350 nm. With Rib waveguides, losses are expected to be even lower. However, in this case the Si reflow during the H2 anneal leads to the formation of a foot at the bottom of the structure and to a rounding of its top. A compromise is thus to be found between low losses and conservation of the rectangular shape of the Rib waveguide. This work proposes to investigate the impact of temperature and duration of the H2 anneal on the Rib profile, sidewalls roughness and optical performances. The impact of a Si/SiO2 interface is also studied. The introduction of H2 thermal annealing allows to obtain very low losses of 0.5 dB/cm at 1310 nm wavelength for waveguide dimensions of 300-400 nm, but it comes along an increase of the pattern bottom width of 41%, with a final bottom width of 502 nm.

Improvement of sidewall roughness of sub-micron silicon-on-insulator waveguides for low-loss on-chip links

We report the successful fabrication of low-loss sub-micrometric Silicon-On-Insulator strip waveguides for on-chips links. Several strategies including post-lithography treatment, and post-Silicon smoothening techniques such as thermal oxidation and hydrogen annealing have been investigated to smoothen the waveguide sidewalls, as roughness is the major source of transmission losses. An extremely low silicon line edge roughness of 0.75nm is obtained with the optimized process flow combining resist mask Si patterning and hydrogen annealing at 850°C. As a result, record low optical losses of less than 0.5dB/cm are measured at 1310nm for waveguide dimensions superior to 500nm. They range from 2dB/cm to 0.8dB/cm for 300-400nm wide waveguides. Those results are to our knowledge the best ever published for a 1310nm wavelength.

Study of selective chemical downstream plasma etching of silicon nitride and silicon oxide for advanced patterning applications

The evolution of integrated components in the semiconductors industry is nowadays looking for ultra-high selective etching processes in order to etch high aspect ratio structures in complicated stacks of ultrathin layers. For ultra-high selective processes, typical plasma etching show limitations, while wet etching processes reach limitations due to capillary forces. For these reasons there is a great regain of interest today in chemical downstream etching systems (CDE), which combine the advantages of plasma and wet treatments. The absence of photons and ions allow to minimize damages and to achieve very high selectivity (in isotropic etching). In this work we investigated the parameters enabling to etch selectively the Si3N4 to the SiO2 by CDE. We shown that the correlation between the gas mixture and the wafer temperature is the key to obtain the desired selectivity. In order to optimize the processing window, the mixture composition (NF3/N2/O2/He) and the temperatures were screened by several DOE (Designs Of Experiments). Conditions are found in which the etching selectivity between the two silicon alloys is higher than 100, which allowed us to clean out sacrificial Si3N4 layers in very high aspect ratio (about 100) silicon trenches of nanometric size (60nm) without damaging the 10nm thin SiO2 caping layer (between the Si and the Si3N4). This demonstrates that downstream plasma etching can perform better than wet treatments in this case.

Plasma etching processes for the integration of InP based compounds on 200mm Si wafer for photonic applications

Ar/Cl2/CH4 gas mixture has been investigated for the development of plasma etching process dedicated to the patterning of 3μm-deep InP structures integrated on 200mm SiO2 carrier wafer. The plasma process requirements are: high InP etch rates (>500nm.min-1), high InP/SiO2 selectivity (<40), anisotropic profiles and smooth bottom and sidewalls surfaces. The process development mainly focuses on the impact of the gas ratio and gas flow on the etch rates, selectivity, pattern profile and surface roughness. It is demonstrated that the CH4 flow drives the process performance and that by adjusting it properly, a narrow process window provides acceptable selectivity of 25, anisotropic profiles and smooth surface. The difficulty of the process development using Ar/Cl2/CH4 gas mixture is to combine high InP/SiO2 selectivity and anisotropic profiles since to passivate efficiently the InP sidewalls and prevent from lateral etching, it seems that a SiOC like deposition is needed, which is only possible if the SiO2 wafer is etched.

MD simulations of chlorine plasmas interaction with ultrathin silicon films for advanced etch processes

Molecular dynamics simulations are performed to study the interaction between chlorine plasmas and ultrathin silicon films under pulsed plasma conditions. The ion energy appears to be the key parameter to control the etch process since both the mixed layer thickness and the etch yield are fairly reduced when the ion energy is decreased from 100eV to 10eV. The neutral-to-ion flux ratio and the neutral dissociation rate also have an impact but to a lesser extent.