Laurent Vallier

Nanometer scale linewidth control during etching of polysilicon gates in high-density plasmas

We address some of the plasma issues encountered for ultimate silicon gate patterning that should be fixed in order to establish the long term viability of plasma processes in integrated circuits manufacturing. For sub-100-nm gate dimensions, one of the main issues is to precisely control the shape of the etched feature. This requires a detailed knowledge of the various physico-chemical mechanisms involved in plasma etching and deposition.

Reducing damage to Si substrates during gate etching processes by synchronous plasma pulsing

Plasma oxidation of the c-Si substrate through a very thin gate oxide layer can be observed during HBr/O2/Ar based plasma overetch steps of gate etch processes. This phenomenon generates the so-called silicon recess in the channel and source/drain regions of the transistors. In this work, the authors compare the silicon recess generated by continuous wave HBr/O2/Ar plasmas and synchronous pulsed HBr/O2/Ar plasmas. Thin SiO2 layers are exposed to continuous and pulsed HBr/O2/Ar plasmas, reproducing the overetch process conditions of a typical gate etch process. Using in situ ellipsometry and angle resolved X-ray photoelectron spectroscopy, the authors demonstrate that the oxidized layer which leads to silicon recess can be reduced from 4 to 0.8 nm by pulsing the plasma in synchronous mode.

Silicon recess minimization during gate patterning using synchronous plasma pulsing

With the emergence of new semiconductor devices and architectures, there is a real need to limit plasma induced damage. This study clearly demonstrates the capability of pulsed plasma technology to minimize plasma induced silicon oxidation that leads to the silicon recess phenomenon during polysilicon gate patterning. Indeed, the authors show that by pulsing optimized continuous wave overetch plasma conditions using HBr/He/O2 plasmas, the silicon recess is reduced from 0.6 to 0.2 nm, while the gate profiles are maintained anisotropic. Synchronous pulsed plasmas open new paths to pattern complex stacks of ultrathin materials without surface damage.

Etching mechanisms of thin SiO2 exposed to Cl2 plasma

Plasma etching is the most standard patterning technology used in micro- and nano-technologies. Chlorine-based plasmas are often used for silicon etching. However, the behavior of thin silicon oxide exposed to such a plasma is still not fully understood. In this paper, we investigate how a thin silicon oxide layer on silicon behaves when it is exposed to a Cl2 plasma. The authors show that chlorine atoms diffuse and/or Cl+ ions are implanted through the thin (<2.5 nm) oxide, leading to the formation of a SiClx interface layer between the two layers of Si and SiO2. Chlorine accumulates at the interface until the SiO2 is thin enough to release volatile SiClx species and the silicon begins to be etched.

Etch mechanisms of silicon gate structures patterned in SF6/CH2F2/Ar inductively coupled plasmas

Patterning complex metal gate stack becomes increasingly challenging since the gate dimension for all isolated as well as dense gate structures present on 300 mm wafer needs to be controlled within the nanometer range. In this article, the authors show that SF6/CH2F2/Ar plasma chemistries to etch the polysilicon gate present very interesting critical dimension (CD) control capabilities for advanced gate etch strategies compared to commonly used HBr/O2/Cl2 plasma chemistries, thanks to the different mechanisms involved in the passivation layer formation on the gate sidewalls. Indeed, contrary to HBr/Cl2/O2 plasma chemistries, the passivation layers in SF6/Ar/CH2F2 plasmas are not formed from deposition of etch by-products coming from the gas phase but the passivating species are chemically sputtered from the bottom of the etched structures and coat the silicon sidewalls by line of sight deposition. Such mechanisms result in thin and uniform CFX passivation layers on the gate sidewalls very similar in dense...

Atomic-scale silicon etching control using pulsed Cl2 plasma

Plasma etching has been a key driver of miniaturization technologies toward smaller and more powerful devices in the semiconductor industry. Thin layers involved in complex stacks of materials are approaching the atomic level. Furthermore, new categories of devices have complex architectures, leading to new challenges in terms of plasma etching. New plasma processes that are capable to etch ultra-thin layers of materials with control at the atomic level are now required. In this paper, the authors demonstrate that Si etching in Cl2 plasma using plasma pulsing is a promising way to decrease the plasma-induced damage of materials. A controlled etch rate of 0.2 nm min−1 is reported by pulsing the chlorine plasma at very low duty cycles. Using quasi-in-situ angle resolved XPS analyses, they show that the surface of crystalline silicon is less chlorinated, the amorphization of the top crystalline silicon surface is decreased, and the chamber wall are less sputtered in pulsed plasmas compared to continuous wave plasmas. This is attributed to the lower density of radicals, lower ion flux, and lower V-UV flux when the plasma is pulsed.

Towards new plasma technologies for 22nm gate etch processes and beyond

Since more than 30 years, CW plasmas have been used in the microelectronics industry to pattern complex stacks of materials involved in Integrated Circuit technologies. Even if miniaturization challenges have been successfully addressed thanks to plasma patterning technologies, several fundamental limitations of the plasmas remain and are limiting our ability to shrink further the device dimensions. In this work, we analyze the capabilities of synchronized pulsed ICP technologies and their potential benefits for front end etch process performance. The impact of duty cycle and frequency on the ion energy distribution function and plasma chemistry is analyzed. Our results show that decreasing the duty cycle in ICP plasmas generates less fragmentation of the feed gas stock molecules compared to CW plasmas, leading in final to a decrease of the radical density in the plasma. On a process point of view, we have studied the etching of ultra-thin layers (SiO2, HfO2,SiN spacer) involved in front end processes and investigated what synchronized pulsed plasmas could bring to substrate damage and selectivity issues.

Silicon gate notching for patterning features with dimensions smaller than the resolution of the lithography

Abstract In less than 10 years, we will be approaching the limits of CMOS technology with transistor gate length between 20 and 30 nm. The definition of the transistor gate region will remain one of the most critical steps of the device fabrication process since the final gate dimension cannot be derived from the dimension targeted by more than few nanometers. Etching of silicon gates is achieved in high density plasmas, allowing vertical profiles to be obtained, transferring the critical dimensions (CD) obtained after lithography. The ultimate resolution of this approach is limited by the lithographic performance of the exposure tool and by the etching process. In the present paper, we present a new type of process allowing the design of gates having a bottom dimension smaller than the top dimension (the so-called ‘notched gate’). We discuss the design of the notched gate process with respect to a standard gate etch process and give some details on the sidewall passivation layer engineering. Finally, some results of CD control across a 200-mm diameter wafer are shown and the potential implementation of the process in pilot lines is discussed.

Overview of several applications of chemical downstream etching (CDE) for IC manufacturing: advantages and drawbacks versus WET processes

Today the IC manufacturing faces lots of problematics linked to the continuous down scaling of printed structures. Some of those issues are related to wet processing, which are often used in the IC manufacturing flow for wafer cleaning, material etching and surface preparation. In the current work we summarize the limitations for the next nodes of wet processing such as metallic contaminations, wafer charging, corrosion and pattern collapse. As a replacement, we promoted the isotropic chemical dry etching (CDE) which is supposed to fix all the above drawbacks. Etching steps of SI3N4 layers were evaluated in order to prove the interest of such technique.

Study of selective chemical downstream plasma etching of silicon nitride and silicon oxide for advanced patterning applications

The evolution of integrated components in the semiconductors industry is nowadays looking for ultra-high selective etching processes in order to etch high aspect ratio structures in complicated stacks of ultrathin layers. For ultra-high selective processes, typical plasma etching show limitations, while wet etching processes reach limitations due to capillary forces. For these reasons there is a great regain of interest today in chemical downstream etching systems (CDE), which combine the advantages of plasma and wet treatments. The absence of photons and ions allow to minimize damages and to achieve very high selectivity (in isotropic etching). In this work we investigated the parameters enabling to etch selectively the Si3N4 to the SiO2 by CDE. We shown that the correlation between the gas mixture and the wafer temperature is the key to obtain the desired selectivity. In order to optimize the processing window, the mixture composition (NF3/N2/O2/He) and the temperatures were screened by several DOE (Designs Of Experiments). Conditions are found in which the etching selectivity between the two silicon alloys is higher than 100, which allowed us to clean out sacrificial Si3N4 layers in very high aspect ratio (about 100) silicon trenches of nanometric size (60nm) without damaging the 10nm thin SiO2 caping layer (between the Si and the Si3N4). This demonstrates that downstream plasma etching can perform better than wet treatments in this case.