Can Çalışkan

A wideband high isolation CMOS T/R switch for X-band phased array radar systems

This paper presents an SPDT switch which is designed to operate at 8-12 GHz frequency range (X-Band), as a sub module of the front end circuit of a phased array radar. The switch distinguishes itself from its counterparts with its larger frequency range and higher isolation that is uniformly distributed over its bandwidth. It is fabricated using 0.25μm SiGe BiCMOS technology of IHP Microelectronics (Germany). As a new technique, shunt inductors are placed next to shunt transistors in order to improve trade-off between insertion loss and isolation. It has isolation higher than 30 dB in entire band, input referred 1dB compression point is 27.6 dBm, insertion loss is between 2.7-4.1 dB, input and output referred return losses are better than 11 dB in the frequency range of 8-12 GHz.

Implementation of TDI based digital pixel ROIC with 15μm pixel pitch

A 15um pixel pitch digital pixel for LWIR time delay integration (TDI) applications is implemented which occupies one fourth of pixel area compared to previous digital TDI implementation. TDI is implemented on 8 pixels with oversampling rate of 2. ROIC provides 16 bits output with 8 bits of MSB and 8 bits of LSB. Pixel can store 75 M electrons with a quantization noise of 500 electrons. Digital pixel TDI implementation is advantageous over analog counterparts considering power consumption, chip area and signal-to-noise ratio. Digital pixel TDI ROIC is fabricated with 0.18um CMOS process. In digital pixel TDI implementation photocurrent is integrated on a capacitor in pixel and converted to digital data in pixel. This digital data triggers the summation counters which implements TDI addition. After all pixels in a row contribute, the summed data is divided to the number of TDI pixels(N) to have the actual output which is square root of N improved version of a single pixel output in terms of signal-to-noise-ratio (SNR).

Phase error reduction of a digitally controlled phase shifter utilizing a variable phase and gain amplifier

This paper presents a variable phase and gain amplifier (VPGA), featured in a 4-bit digitally controlled phase shifter, that enables significant phase error reduction. The functionality of the VPGA is demonstrated by utilizing it between the third and fourth bits of a digitally controlled phase shifter. The first three bits are implemented using distributed active switches based on HBTs and the fourth bit is realized in a final amplification stage based on switching between common-base (CB) and common-emitter (CE) topologies. By the use of the VPGA, RMS phase error is reduced from 22° to 11° with the cost of reduced gain (0.1-2.5dB) and increased RMS gain error (1.0-2.2dB). A total of 360° phase shift is achieved in 4bit resolution with an RMS phase error of 0.1° at 10.5GHz, and a maximum 11° phase error in 4.5GHz bandwidth. The chip area is 2.150mm×1.040mm including pads, and the VPGA consumes only 0.32mm×0.410mm area. The chip is implemented in a 0.25-źm SiGe BiCMOS process. These performance parameters are attributed to the adjustment method by the VPGA applied in this work, which enables superior performance than the-state-of-the-art utilizing similar technologies.