Cândido Duarte

Basic analog circuits with a-GIZO thin-film transistors: Modeling and simulation

This paper addresses a modeling and simulation methodology for analog circuit design with amorphous-GIZO thin-film transistors (TFTs). To reach an effective circuit design flow, with commercially available tools, a TFT model has been first developed with an artificial neural network (ANN). Multilayer perceptron with backpropagation algorithm has been adopted to model the static behavior of the TFT devices, for different aspect ratios. The model was then implemented in Verilog-A, to allow a quick instantiation in circuit. Simulations using Cadence Spectre are performed to validate the model. On a second phase, simulation results of basic analog circuits, with this ANN model, are verified against the actual functional results, namely an adder, subtractor, and current mirror circuit. Results demonstrate not only the ANN model accuracy and compatibility with dc and transient analysis, but also show the a-GIZO TFT capability to perform analog operations.

Network infrastructure for academic IC CAD environments

This paper presents an initiative to involve ECE undergraduate students in the design and deployment of a network infrastructure for an academic laboratory. The project aims at attaining a reliable and secure network for an IC CAD environment. The students focused on employing secure authentication, accounting and storage with single sign-on, based on enterprise-grade, open-source protocols. This initiative proved to be highly motivating and allowed the students to develop knowledge and hands-on experience on the area of network security. The resulting network design and core infrastructure is herein described as well as its deployment in a real microelectronics design environment.

Yield Prediction With a New Generalized Process Capability Index Applicable to Non-Normal Data

Monte Carlo (MC) techniques are widely applied to check a design on its robustness and for estimating the production yield of integrated circuits. Using standard random MC and the sample yield for estimation, a very large number of samples is required for accurate verification, especially if a high yield is desired. This can make MC extremely time consuming, but if the data follows a normal Gaussian distribution a much faster yield prediction is possible by using the well-known CPK method. We extended this specification-distance-based scheme for the far more difficult general non-normal case by three different means, ending up in a new generalized process capability index named CGPK. First, we apply parametric modeling only to the specification-sided distribution part. This way any difficulties in distribution parts that actually have little yield impact do not degrade the model fit anymore. Second, to improve the parametric model we introduce a new tail parameter t. Third, to allow modeling of difficult asymmetrical, multimodal or flat distributions we also introduce a new reference location parameter instead of using the mean. An advantage of improving MC this way is that-in opposite to many other MC enhancements (like importance sampling)-the performance of the CGPK is not negatively impacted by design complexity. We described the formulation of the CGPK and derived confidence intervals using an advanced bootstrap scheme. We verified the performance against the sample yield and CPK for a representative set of distributions, including real production data and MC data from the design of a CMOS operational amplifier and other circuits.

Multipliers with transparent a-GIZO TFTs using a neural model

This paper presents the results of a preliminary study to examine the ability of post-silicon devices for analog processing. It is focused on the latest thin-film transistors (TFTs) with amorphous gallium-indium-zinc oxide (a-GIZO) as active layer. Three circuit configurations are presented: a differential pair and two multiplier topologies. Both triode and saturation regions of operation are included in the analysis, with the devices set to remain in strong accumulation. A neural model, which is developed based on the measured data of the TFTs, is used for the circuit simulations in the Cadence Virtuoso environment. The analog multipliers simulation results are compared against the expected functional results.

An energy study on IR-UWB transmitter using integration-and-fire modulation

The integrate-and-fire model of a biological neuron is an amplitude to time encoding in the spacing between action potentials (spikes). In principle, this encoding can be used to modulate signals in an Impulse Radio Ultra Wide-Band (IR-UWB) transmitter suitable for Wireless Sensor Networks (WSN). This paper presents a system level study on power efficiency using MATLAB/Simulink to evaluate the required energy for an IR-UWB Transmitter using integrate-and-fire encoding technique. Also, a simple but clear comparison with common systems utilizing Nyquist rate Analog-to-Digital Converters (ADC) is presented. This study has been carried out on a band-limited random Gaussian signal and the results show that IR-IF transmitter consumes roughly seven times less energy than a digital UWB transmitter; moreover, in the proposed architecture the need for power hungry ADC is relaxed.

Performance Improvement of a Buck Converter using Kalman Filtering

This paper presents a predictive current control algorithm for a synchronous buck converter using an extended Kalman filter (EKF) algorithm. The predictive approach avoids the need of current-sensing circuitry and provides insensitivity to Gaussian noise sources at the output of the buck converter, which is the same as the control loop input. The method requires a model for the buck converter, the EKF design, and current loop tuning. All these prerequisites are described in this work along with the implementation of the algorithm in a state of the art microcontroller. Simulation and experimental results show that while maintaining a good step response, the proposed method provides better results than standard methods when Gaussian noise is present at the output voltage.

Filter & hold: a mixed continuous‐/discrete‐time technique for time‐constant scaling

SUMMARY The work reported in this paper introduces a periodic switching technique applied to continuous-time filters, whose outcome is an equivalent filter with scaled time-constants. The principle behind the method is based on a procedure that extends the integration time by periodically interrupting the normal integration of the filter. The net result is an up scaling of the time constant, inversely proportional to the switching duty-cycle. This is particularly suitable for reducing the area occupied by passive devices in integrated circuits, as well as to accurately calibrate the filter dynamics. Previous works have been following this concept in an entirely continuous-time perspective, either focusing on specific circuits or using approximations to provide an extended analysis. This paper includes input/output sampling to derive a closed-form representation for the scaling technique herein coined as ‘Filter & Hold’ (F&H). A detailed mathematical analysis is described, demonstrating that the F&H concept represents an exact filtering solution. Simulation results and experimental measurements are provided to further validate the theoretical analysis for an F&H vector-filter prototype. Copyright

BIST design for analog cell matching

This work addresses a built-in self-test methodology for circuit cell identification under specific matching conditions. The proposed technique is applied to the CMOS realization of a reduced-KII network, which is a system model of the biological olfactory cortex. This model behaves as an associative memory, a useful tool for information and adaptive processes. Based on a mixed-signal approach, the test strategy makes proper use of the circuits comprising the network structure, and provides self reconfiguration as well. Both testing procedures and design of essential building blocks are described in this paper. Simulation results are presented for a reduced-KII network comprising 128-cells, sequentially tested for matching in terms of offsets and their dynamic performances.