Pedro Guedes de Oliveira

Transparent Current Mirrors With a-GIZO TFTs: Neural Modeling, Simulation and Fabrication

This paper characterizes transparent current mirrors with n-type amorphous gallium-indium-zinc-oxide (a-GIZO) thin-film transistors (TFTs). Two-TFT current mirrors with different mirroring ratios and a cascode topology are considered. A neural model is developed based on the measured data of the TFTs and is implemented in Verilog-A; then it is used to simulate the circuits with Cadence Virtuoso Spectre simulator. The simulation outcomes are validated with the fabricated circuit response. These results show that the neural network can model TFT accurately, as well as the current mirroring ability of the TFTs.

Basic analog circuits with a-GIZO thin-film transistors: Modeling and simulation

This paper addresses a modeling and simulation methodology for analog circuit design with amorphous-GIZO thin-film transistors (TFTs). To reach an effective circuit design flow, with commercially available tools, a TFT model has been first developed with an artificial neural network (ANN). Multilayer perceptron with backpropagation algorithm has been adopted to model the static behavior of the TFT devices, for different aspect ratios. The model was then implemented in Verilog-A, to allow a quick instantiation in circuit. Simulations using Cadence Spectre are performed to validate the model. On a second phase, simulation results of basic analog circuits, with this ANN model, are verified against the actual functional results, namely an adder, subtractor, and current mirror circuit. Results demonstrate not only the ANN model accuracy and compatibility with dc and transient analysis, but also show the a-GIZO TFT capability to perform analog operations.

High-gain amplifier with n-type transistors

A high-gain amplifier topology, with all single n-type enhancement transistors, is proposed in this paper. This type of circuits are essential in transparent TFT technologies, such as GIZO and ZnO that lack complementary type transistor. All circuits were simulated using BSIM3V3 model of a 0.35 μm CMOS technology, due to the absence of a complete electrical model for the TFTs. Results reveal that the proposed circuit promise more gain, lower power consumption and higher bandwidth than the existing solutions under identical bias conditions.

InGaZnO Thin-Film-Transistor-Based Four-Quadrant High-Gain Analog Multiplier on Glass

This letter presents a novel high-gain four-quadrant analog multiplier using only n-type enhancement indium-gallium-zinc-oxide thin-film-transistors. The proposed circuit improves the gain by using an active load with positive feedback. A Gilbert cell with a diode-connected load is also presented for comparison purposes. Both circuits were fabricated on glass at low temperature (200°C) and were successfully characterized at room temperature under normal ambient conditions, with a power supply of 15 V and 4-pF capacitive load. The novel circuit has shown a gain improvement of 7.2 dB over the Gilbert cell with the diode-connected load. Static linearity response, total harmonic distortion, frequency response, and power consumption are reported. This circuit is an important signal processing building block in large-area sensing and readout systems, specially if data communication is involved.

Network infrastructure for academic IC CAD environments

This paper presents an initiative to involve ECE undergraduate students in the design and deployment of a network infrastructure for an academic laboratory. The project aims at attaining a reliable and secure network for an IC CAD environment. The students focused on employing secure authentication, accounting and storage with single sign-on, based on enterprise-grade, open-source protocols. This initiative proved to be highly motivating and allowed the students to develop knowledge and hands-on experience on the area of network security. The resulting network design and core infrastructure is herein described as well as its deployment in a real microelectronics design environment.

Multipliers with transparent a-GIZO TFTs using a neural model

This paper presents the results of a preliminary study to examine the ability of post-silicon devices for analog processing. It is focused on the latest thin-film transistors (TFTs) with amorphous gallium-indium-zinc oxide (a-GIZO) as active layer. Three circuit configurations are presented: a differential pair and two multiplier topologies. Both triode and saturation regions of operation are included in the analysis, with the devices set to remain in strong accumulation. A neural model, which is developed based on the measured data of the TFTs, is used for the circuit simulations in the Cadence Virtuoso environment. The analog multipliers simulation results are compared against the expected functional results.

Filter & hold: a mixed continuous‐/discrete‐time technique for time‐constant scaling

SUMMARY The work reported in this paper introduces a periodic switching technique applied to continuous-time filters, whose outcome is an equivalent filter with scaled time-constants. The principle behind the method is based on a procedure that extends the integration time by periodically interrupting the normal integration of the filter. The net result is an up scaling of the time constant, inversely proportional to the switching duty-cycle. This is particularly suitable for reducing the area occupied by passive devices in integrated circuits, as well as to accurately calibrate the filter dynamics. Previous works have been following this concept in an entirely continuous-time perspective, either focusing on specific circuits or using approximations to provide an extended analysis. This paper includes input/output sampling to derive a closed-form representation for the scaling technique herein coined as ‘Filter & Hold’ (F&H). A detailed mathematical analysis is described, demonstrating that the F&H concept represents an exact filtering solution. Simulation results and experimental measurements are provided to further validate the theoretical analysis for an F&H vector-filter prototype. Copyright

Transparent Current Mirrors Using a-GIZO TFTs: Simulation with RBF Models and Fabrication

This paper analyzes transparent two-TFT current mirrors using a-GIZO TFTs with different mirroring ratios. In order to achieve a high mirroring ratio, the output TFT in the circuit employed a fingered structure layout to minimize area and overlap capacitance. The analysis of the current mirrors is performed in three phases. In the first, a radial basis function based (RBF) model is developed using measured data from fabricated TFTs on the same chip. Then, in the second phase, the RBF model is implemented in Verilog-A that is used to simulate two-TFT current mirrors with different mirroring ratios. The simulations are carried out using Cadence spectre simulator. In the third phase, simulation results are validated with the measured response from the fabricated circuits.

BIST design for analog cell matching

This work addresses a built-in self-test methodology for circuit cell identification under specific matching conditions. The proposed technique is applied to the CMOS realization of a reduced-KII network, which is a system model of the biological olfactory cortex. This model behaves as an associative memory, a useful tool for information and adaptive processes. Based on a mixed-signal approach, the test strategy makes proper use of the circuits comprising the network structure, and provides self reconfiguration as well. Both testing procedures and design of essential building blocks are described in this paper. Simulation results are presented for a reduced-KII network comprising 128-cells, sequentially tested for matching in terms of offsets and their dynamic performances.