Jerry Hallmark

Field effect transistors with SrTiO3 gate dielectric on Si

SrTiO3 has been grown epitaxially by molecular beam epitaxy on Si. The capacitance of this 110 A dielectric film is electrically equivalent to less than 10 A of SiO2. This structure has been used to make capacitors and metal oxide semiconductor field effect transistors. The interface trap density between the SrTiO3 and the Si is 6.4×1010 states/cm2 eV and the inversion layer mobility is 221 and 62 cm2/V s for n- and p-channel devices, respectively. The gate leakage in these devices is two orders of magnitude smaller than a similar SiO2 gate dielectric field effect transistor.

Epitaxial oxide thin films on Si(001)

Over the years, the development of epitaxial oxides on silicon has been a great technological challenge. Amorphous silicon oxide layer forms quickly at the interface when the Si surface is exposed to oxygen, making the intended oxide heteroepitaxy on Si substrate extremely difficult. Epitaxial oxides such as BaTiO3 (BTO) and SrTiO3 (STO) integrated with Si are highly desirable for future generation transistor gate dielectric and ferroelectric memory cell applications. In this article, we review the recent progress in the heteroepitaxy of oxide thin films on Si(001) substrate by using the molecular beam epitaxy technique at Motorola Labs. Structural, interfacial and electrical properties of the oxide thin films on Si have been characterized using in situ reflection high energy electron diffraction, x-ray diffraction, spectroscopic ellipsometry, atomic force microscopy, Auger electron spectroscopy, x-ray photoelectron spectroscopy, high-resolution transmission electron microscopy, high-resolution transmissi...

A manufacturable complementary GaAs process

A self-aligned complementary GaAs heterostructure FET process has been established for low power, high-speed digital circuits. The devices are fabricated on four-inch MBE epitaxial wafers consisting of AlGaAs/InGaAs epilayers grown on LEC GaAs substrates. The process uses twelve lithographic steps including two levels of interconnect metal. Typical transconductances of 250 mS/mm and 60 mS/mm are achieved on 1/spl times/10 /spl mu/m N-channel and P-channel devices, respectively. Twenty-three stage unloaded complementary ring oscillators consisting of 1/spl times/10 /spl mu/m N- and P-FETs show propagation delay of 190 ps and speed-power product of 7.5 fJ or 0.35 /spl mu/W/MHz.<<ETX>>

Epitaxial perovskite thin films grown on silicon by molecular beam epitaxy

Thin film perovskite-type oxide SrTiO3 has been grown epitaxially on Si(001) substrate by molecular beam epitaxy. Reflection high energy electron diffraction and x-ray diffraction analysis indicate high quality SrTiO3 heteroepitaxy on Si substrate with SrTiO3(001)//Si(001) and SrTiO3[010]//Si[110]. The SrTiO3 surface is atomically as smooth as the starting substrate surface, with a root mean square roughness of 1.2 A observed by atomic force microscopy. The thickness of the amorphous interfacial layer between SrTiO3 and Si has been engineered to minimize the device short channel effect. An effective oxide thickness <10 A has been obtained for a 110 A thick dielectric film. The interface state density between SrTiO3 and Si is 6.4×1010 cm−2 eV−1, and the inversion layer carrier mobilities are 221 and 62 cm2 V−1 s−1 for n- and p-channel metal–oxide–semiconductor devices with 1.2 μm effective channel length, respectively. The gate leakage in these devices is two orders of magnitude smaller than a comparable S...

Interface characterization of high-quality SrTiO3 thin films on Si(100) substrates grown by molecular beam epitaxy

Single-crystal SrTiO3 has been grown on Si(100) using molecular beam epitaxy (MBE). The growth conditions, especially at the initial stage of nucleation, have a great impact on the SrTiO3/Si interface. A regrowth of an amorphous interfacial layer as thick as 23 A has been observed and identified as a form of SiOx. This is a direct result of an internal oxidation during the growth of the STO film due to the oxygen diffusion and reaction with the silicon substrate at the interface. The optimization of the deposition process in terms of growth temperature and oxygen partial pressure has led to an interfacial layer as thin as 11 A. Metal oxide semiconductor (MOS) capacitors with an equivalent oxide thickness tox of 12 A and a leakage current of 2×10−4 A/cm2 have been obtained for a 50 A SrTiO3.

Developing micro-fuel cells for wireless communications

Abstract Energy needs for portable electronics are rising beyond what batteries can manage, so there is great interest in investigating what fuel cells can bring to this potentially enormous market. This article reports on how Motorola Labs has been developing direct methanol fuel cells in the 100 mWe to 1 We range, for use in portable wireless communications in particular.

Properties of Epitaxial SrTiO 3 Thin Films Grown on Silicon by Molecular Beam Epitaxy

Single crystalline perovskite oxides such as SrTiO 3 (STO) are highly desirable for future generation ULSI applications. Over the past three decades, development of crystalline oxides on silicon has been a great technological challenge as an amorphous silicon oxide layer forms readily on the Si surface when exposed to oxygen preventing the intended oxide heteroepitaxy on Si substrate. Recently, we have successfully grown epitaxial STO thin films on Si(001) surface by using molecular beam epitaxy (MBE) method. Properties of the STO films on Si have been characterized using a variety of techniques including in-situ reflection high energy electron diffraction (RHEED), ex-situ X-ray diffraction (XRD), spectroscopic ellipsometry (SE), Auger electron spectroscopy (AES) and atomic force microscopy (AFM). The STO films grown on Si(001) substrate show bright and streaky RHEED patterns indicating coherent two-dimensional epitaxial oxide film growth with its unit cell rotated 450 with respect to the underlying Si unit cell. RHEED and XRD data confirm the single crystalline nature and (001) orientation of the STO films. An X-ray pole figure indicates the in-plane orientation relationship as STO[100]//Si[110] and STO(001)// Si(001). The STO surface is atomically smooth with AFM rms roughness of 1.2 AA. The leakage current density is measured to be in the low 10 −9 A/cm 2 range at 1 V, after a brief post-growth anneal in O 2 . An interface state density D it = 4.6 × 10 11 eV −1 cm −2 is inferred from the high-frequency and quasi-static C-V characteristics. The effective oxide thickness for a 200 A STO film is around 30 A and is not sensitive to post-growth anneal in O 2 at 500-700°C. These STO films are also robust against forming gas anneal. Finally, STO MOSFET structures have been fabricated and tested. An extrinsic carrier mobility value of 66 cm 2 V −1 1 s −1 is obtained for an STO PMOS device with a 2 μm effective gate length.

0.9 V DSP blocks: a 15 ns 4 K SRAM and a 45 ns 16-bit multiply/accumulator

4-k SRAM and 16-b multiply/accumulate DSP blocks have been designed and fabricated in complementary heterostructure GaAs. Both circuits operate from 1.5 V to below 0.9 V. The SRAM uses 28,272 transistors in an area of 2.44 mm/sup 2/. Cell size is 278 /spl mu/m/sup 2/ at 1.0-/spl mu/m gate length. Measured results show an access delay of 5.3 ns at 1.5 V and 15.0 ns at 0.9 V. At 0.9 V, the power dissipated is 0.36 mW. The CGaAs multiplier uses a 16-b modified Booth architecture with a 3-way 40-b accumulator. The multiplier uses 11,200 transistors in an area of 1.23 mm/sup 2/. Measured delay is 19.0 ns at 1.5 V and 44.7 ns at 0.9 V. At 0.9 V, current is less than 0.4 mA. >

Epitaxial Oxide Films on Silicon: Growth, Modeling and Device Properties

Using molecular beam epitaxy, thin films perovskite-type oxide Sr x Ba 1−x TiO 3 (0≤×≤1) has been grown epitaxially on Si(001) substrates. Reflection high energy electron diffraction measurements and X-ray diffraction analysis indicate that high quality heteroepitaxy on Si takes place with Sr x Ba 1−x TiO 3 (001)//Si(001) and Sr x Ba 1−x TiO 3 [010]//Si[10]. Extensive atomic simulations have been carried out to understand the initial growth mechanism of the oxide layers on silicon. SrTiO 3 layers grown directly on Si have been used as the gate dielectric for the fabrication of MOSFET devices. By varying the growth conditions the thickness of the amorphous interfacial silicon oxide layer formed during the growth of the oxide layers has been engineered to minimize the device short channel effects. An effective oxide thickness 3 dielectric film with interface state density around 6.4 × 10 10 cm −2 e V-1 , and the inversion layer carrier mobilities of 220 cm 2 V −1 s −1 and 62 cm 2 V −l s −1 for NMOS and PMOS devices, respectively. The gate leakage in these devices is 2 orders of magnitude smaller than a comparable SiO 2 gate dielectric MOSFET.

Bismuth based layered perovskite thin films as a charge storage material for low power nonvolatile gaas memory applications

Abstract This work details initial process development and integration of ferroelectric SrBi2Ta2O9 and SrBi2Ta2(1-x)Nb2xO9 for use in low power nonvolatile GaAs memory technology. A spin on process is used to deposit the ferroelectric thin films. Capacitance, hysteresis loop, and switched charge versus time data are presented for metal-ferroelectric-metal capacitors using platinum as the electrode material. Indications are that the substitution of niobium for tantalum in the layered perovskite structure increases both the non-volatile polarization and the coercive field of the material. N-channel transistor characteristics of the low power gallium arsenide field effect transistor contained in the 1T-1C memory bit are also presented. The results presented here imply that these materials warrant further research and process integration studies to realize low power non-volatile GaAs memory technology.