Carl W. Moreland

A 14-bit 100-Msample/s subranging ADC

This paper describes a 14-b analog-to-digital converter designed in a complementary bipolar process. Although it uses a fairly traditional three-stage subranging architecture, several nontraditional techniques are incorporated to achieve 14 bits of performance at a clock rate of 100 MHz. For linearity, the most critical of these is wafer level trimming of the first subrange digital-to-analog converter. Prototype silicon exhibits a spurious-free dynamic range of 90 dB through the Nyquist frequency and a signal-to noise ratio of 74 dB while dissipating 1.25 W.

A 14b 100MSample/s 3-stage A/D converter

A 14b three-stage ADC uses a complementary bipolar process to achieve a 100MSample/s encode rate with a SFDR of >90 dB and an SNR of 75 dB. While the design is based on a traditional multi-stage architecture, the three encoder stages use serial-ripple converters. Unlike the typical N-bit flash converter which requires 2-/sup N-1/ comparators, the serial-ripple converter has only N comparators. The result is a smaller die area and lower power dissipation than flash. This design uses a total of 16 comparators, and at the full sample rate consumes 1250 mW. It is fabricated in a 0.8 /spl mu/m double-poly complementary bipolar process.

A dual channel IF-digitizing IC with 117dB dynamic range at 300Mhz IF for EDGE/GSM base-stations [receiver]

An integrated circuit is presented which receives an input IF frequency in the range of 70-300 MHz, and achieves 117 dB of dynamic range in a 200 kHz bandwidth (BW). An automatic-gain-control (AGC) loop is placed around the analog-to-digital converter (ADC). Amplitude-modulation (AM) caused by gain switching is corrected digitally.