Carlos Arthur Lang Lisbôa

System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies

The evolution of the technology in search of smaller and faster devices brings along the need for a new paradigm in the design of circuits tolerant to soft errors. The current assumption of transient pulses shorter than the cycle time of the circuit will no longer be true, thereby precluding the use of most of the mitigation techniques proposed so far. With transient faults duration spanning more than one clock cycle of operation, new fault tolerance solutions, working at the system level, with low area and performance overheads, must be devised. In this paper we propose the first steps in the direction of using low cost verification schemes at the algorithmic level, applied to general purpose matrix multiplication applications. Experimental results obtained with two different implementations of checker circuits using the proposed technique are presented and discussed.

Using built-in sensors to cope with long duration transient faults in future technologies

Transients spanning more than one clock cycle will challenge soft error tolerant designs for future technologies. To face this problem, a low overhead technique that uses bulk built-in current sensors and recomputation is proposed here.

New Techniques for Improving the Performance of the Lockstep Architecture for SEEs Mitigation in FPGA Embedded Processors

The growing availability of embedded processors inside FPGAs provides unprecedented flexibility for system designers. The use of such devices for space or mission critical applications, however, is being delayed by the lack of effective low cost techniques to mitigate radiation induced errors. In this paper a non invasive approach for the implementation of fault tolerant systems based on COTS processors embedded in FPGAs, using lockstep in conjunction with checkpoint and rollback recovery, is presented. The proposed approach does not require modifications in the processor architecture or in the application software. The experimental validation of this approach through fault injection is described, the corresponding results are discussed, and the addition of a write history table as a means to reduce the performance overhead imposed by previous implementations is proposed and evaluated.

Going beyond TMR for protection against multiple faults

Future technologies will present devices so small that they will be heavily influenced by electromagnetic noise and SEU induced errors. Since many soft errors might appear at the same time, classical fault tolerance techniques, such as TMR, will no longer provide reliable protection and will make new design approaches necessary. This study shows that the TMR approach has intrinsic weaknesses that impair its effectiveness in the presence of multiple faults, and proposes a new technique that provides better protection than TMR for single as well as multiple faults. The proposed technique is based on the use of some analog components among the digital circuits. We present results based on a multiplier, and show that the technique is scalable to withstand higher quantities of simultaneous faults.

Single element correction in sorting algorithms with minimum delay overhead

A low delay overhead technique for the correction of errors affecting sorting algorithms, based on the use of Hamming code, is presented. Given the number of values to be sorted the expected Hamming check bits (as SUMs) are calculated, and a checker technique performs single error correction with lower delay overhead than classic approaches based on algorithm redundancy. The proposed technique has been applied to the well known bubble sorting with different sets of values to be sorted and the comparison of the resulting overhead with that imposed by the classic duplication with comparison and triple modular redundancy techniques shows that it requires lower delay overhead while providing enhanced error correction capabilities.

Arithmetic operators robust to multiple simultaneous upsets

Future technologies, below 90 nm, will present transistors so small that they will be heavily influenced by electromagnetic noise and SEU induced errors. This way, together with process variability, design as known today is likely to change. Since many soft errors might appear at the same time, a different design approach must be taken. The use of inherently robust operators as an alternative to conventional digital arithmetic operators is proposed in this study. The behavior of the proposed operators is analyzed through the simulation of single and multiple random faults injection, and it is shown to be adequate for several classes of applications, standing to multiple simultaneous upsets. The number of tolerated upsets varies according to the number of extra bits appended to the operands, and is limited only by the area restriction. For example, in a multiplier with 2 extra bits per operand, one can obtain robustness against up to 15 simultaneous faults.

A fast error correction technique for matrix multiplication algorithms

Temporal redundancy techniques will no longer be able to cope with radiation induced soft errors in technologies beyond the 45 nm node, because transients will last longer than the cycle time of circuits. The use of spatial redundancy techniques will also be precluded, due to their intrinsic high power and area overheads. The use of algorithm level techniques to detect and correct errors with low cost has been proposed in previous works, using a matrix multiplication algorithm as the case study. In this paper, a new approach to deal with this problem is proposed, in which the time required to recompute the erroneous element when an error is detected is minimized.

XOR-Based Low Cost Checkers for Combinational Logic

Radiation induced transient faults, formerly a concern mainly for memory devices, became one important element contributing to the increase of SER of combinational logic too. Conventional mitigation techniques based on time or space redundancy, either will no longer cope with the long duration transient faults predicted for future technologies, or impose heavy penalties in terms of area, power, and/or performance. In such scenario, the development of new low cost techniques to detect transient faults in combinational logic is a mandatory issue. This paper proposes one alternative for the implementation of XOR-based low cost checkers for combinational circuits, able to detect errors with much less overhead than conventional techniques.

A soft error robust and power aware memory design

A new RAM design, which is soft error robust and power aware, is proposed. The basic advantage of the proposed architecture is that it does achieve a considerable power saving potential, combined with potential for performance and reliability enhancements, while imposing an acceptable area overhead. Analytical models of the proposed architecture are presented and discussed.

Decimal Hamming: A Software-Implemented Technique to Cope with Soft Errors

A low-overhead technique for correction of induced errors affecting algorithms and their data based on the concepts behind Hamming code is presented and evaluated. We go beyond Hamming code by computing the check digits as decimal sums, and using a checker algorithm to perform single error detection and correction and double error detection. This generalization allows for the protection of complex data structures, providing lower performance overhead than classic approaches based on algorithm redundancy, and has been successfully applied to different benchmarking algorithms and their associated data. Comparison of the resulting overheads with those imposed by the classic duplication with comparison shows that the proposed technique, named Decimal Hamming, imposes lower execution time and program memory overheads, while providing enhanced error correction capabilities.