Ronaldo Rodrigues Ferreira

Neutron-Induced Soft Errors in Graphic Processing Units

This paper presents and analyzes the results of neutron experiments on 40nm Graphic Processing Units. We have measured the internal memory resources cross sections, and define a new threads cross section to characterize the computing units sensitivity to radiation. We experimentally evaluate the matrix multiplication application error rate and built an analytical model to predict algorithms neutron-induced failures.

Neutron radiation test of graphic processing units

This paper reports and analyzes the results of neutrons radiation testing campaigns on a modern commercial-off-the-shelf Graphic Processing Unit (GPU). A set of guidelines for accelerated radiation experiments on CPUs is presented, emphasizing the shrewdness necessary to ease the test and gain meaningful data. Radiation test results are presented and discussed, highlighting the neutrons sensitivities of the different GPU memory and logic resources in terms of Failure In Time (FIT) due to neutrons at sea level.

Decimal Hamming: A Software-Implemented Technique to Cope with Soft Errors

A low-overhead technique for correction of induced errors affecting algorithms and their data based on the concepts behind Hamming code is presented and evaluated. We go beyond Hamming code by computing the check digits as decimal sums, and using a checker algorithm to perform single error detection and correction and double error detection. This generalization allows for the protection of complex data structures, providing lower performance overhead than classic approaches based on algorithm redundancy, and has been successfully applied to different benchmarking algorithms and their associated data. Comparison of the resulting overheads with those imposed by the classic duplication with comparison shows that the proposed technique, named Decimal Hamming, imposes lower execution time and program memory overheads, while providing enhanced error correction capabilities.

Exploiting the model-driven engineering approach to improve design space exploration of embedded systems

This paper proposes a design space abstraction, in order to decouple the exploration algorithm from the design space, which allows the application of the design space exploration (DSE) tool in different design scenarios and is appropriate for representing simultaneous and interdependent design alternative. From this new abstraction, the Model-Driven Engineering (MDE) approach is exploited to extract design information and compose the design space to be explored. Our approach uses model-to-model transformation rules as DSE constraints, which prune the available design space. These constraints are automatically generated from the UML model by translating design decisions pre-specified in UML diagrams into model transformation rules. In addition, non-functional requirements specified in UML as stereotypes are used to generate constraints in order to remove invalid solutions proposed during the DSE process. Finally, our approach offers an easy way for the designer to extend the set of constraints by using a well-accepted MDE toolset. A real application running on top of an MPSoC is used as case study to illustrate the proposed method.

Compiler Optimizations Do Impact the Reliability of Control-Flow Radiation Hardened Embedded Software

This paper characterizes how compiler optimizations impact software control-flow reliability when the optimized application is compiled with a technique to enable the software itself to detect and correct radiation induced soft-errors occurring in branches. Supported by a comprehensive fault injection campaign using an established benchmark suite in the embedded systems domain, we show that the careful selection of the available compiler optimizations is necessary to avoid a significant decrease of software reliability while sustaining the performance boost those optimizations provide.

Automatic code generation and solution estimate for object-oriented embedded software

This work tailors an Alloy model translator to Java code and an estimate tool for physical resources optimization into a design-flow. Experimental results show distinct implementation strategies only varying data structures used in generated Java code.

Adaptive Low-Power Architecture for High-Performance and Reliable Embedded Computing

This paper presents the Matrix Operation Microprocessor Architecture (MoMa) for reliable embedded computing. MoMa introduces a software execution mechanism based on transactions, which provides a localized error correction scheme that leads to reduced error correction latency and hardware redundancy without incurring on expensive execution check pointing. Coupled to the transactional software execution is a dedicated adaptive core for matrix multiplication which is protected with a hardware implementation of the Algorithm-Based Fault Tolerance technique. MoMa drives the matrix core in an adaptive fashion based on dynamically turning it on only when high-performance computation is necessary, leading to ultimate power savings and error coverage. We performed an exhaustive FPGA-implemented fault injection campaign, in which we observed an error detection coverage of almost 100% and an error correction coverage of almost 98% on average. MoMa is also evaluated in terms of power, area, and performance, showing its competitiveness against a classical TMR solution.

Adaptive parallelism exploitation under physical and real-time constraints for resilient systems

This paper introduces the Resilient Adaptive Algebraic Architecture, which is capable of adapting parallelism exploitation in a time-deterministic fashion to reduce power consumption, while meeting the existing real-time deadlines. Furthermore, the architecture provides low overhead error correction capabilities, through the use of algebraic properties of the operations it performs. We use two real-time industrial case studies to validate the architecture and to show how the adaptive exploitation works. Finally, we present the results of fault-injection campaigns to show the architecture resilience against soft-errors.

Live-Out Register Fencing: Interrupt-Triggered Soft Error Correction Based on the Elimination of Register-to-Register Communication

This article introduces Live-Out Register Fencing (LoRF), a soft error correction mechanism that uses the novel Spill Register File as a container of checkpointing data. LoRF’s Spill Register File holds the values shared among basic blocks in the program, and, coupled with a new compilation strategy, LoRF allows for error correction in the same basic block where the error was detected. In LoRF, error correction is triggered by a hardware interrupt that restores the registers of a basic block from the Spill Register File. After these registers are restored, the basic block where the error was detected can just be re-executed, thus reducing the costs of error recovery. LoRF’s error correction policy eliminates the need for expensive architectural support for checkpointing and rollback, reducing the performance overhead of online soft error correction. LoRF relies on both a modified processor architecture and a corresponding compiler. The architecture was implemented in synthesizable VHDL, whereas the compiler was developed as an extension of the LLVM framework. Fault injection experiments support an error correction coverage of 99.35% and a mean performance overhead of 1.33 for the entire life cycle of an error from its occurrence to its elimination from the system.

Adaptive Parallelism Exploitation under Physical and Real-Time Constraints for Resilient Systems

This article introduces the resilient adaptive algebraic architecture that aims at adapting parallelism exploitation of a matrix multiplication algorithm in a time-deterministic fashion to reduce power consumption while meeting real-time deadlines present in most DSP-like applications. The proposed architecture provides low-overhead error correction capabilities relying on the hardware implementation of the algorithm-based fault-tolerance method that is executed concurrently with matrix multiplication, providing efficient occupation of memory and power resources. The Resilient Adaptive Algebraic Architecture (RA3) is evaluated using three real-time industrial case studies from the telecom and multimedia application domains to present the design space exploration and the adaptation possibilities the architecture offers to hardware designers. RA3 is compared in its performance and energy efficiency with standard high-performance architectures, namely a GPU and an out-of-order general-purpose processor. Finally, we present the results of fault injection campaigns in order to measure the architecture resilience to soft errors.