Pietro Maris Ferreira

A g m /I D -Based Noise Optimization for CMOS Folded-Cascode Operational Amplifier.

Noise optimization is a challenging problem for nanoscale metal-oxide-silicon field-effect transistor circuits. This brief presents a technique that uses transconductance-to-drain current (gm/ID)-dependent transistor-noise parameters to explore the design space and to evaluate tradeoff decisions. An expression for the corner frequency of the folded-cascode amplifier is derived. The design process demonstrated in this brief using the folded-cascode amplifier is applicable to a wide class of amplifier circuits.

CMOS 65 nm wideband LNA reliability estimation

Radio frequency (RF) products are very demanding in terms of technology developments. Reliability will be one of the most important challenges for the semiconductor industry during the following years. This work presents a wideband low noise amplifier (WBLNA) designed in CMOS 65 nm, its model for reliability estimation, and simulated results of fresh and aged devices. The WBLNA failure, defined in this work as the amount of degradation to have 3 dB gain loss or 10% bandwidth reduction, has been found for HCI ID, SBD and EM degradations. The most important simulated reliability degradation results have been highlighted. Therefore, the design for reliability concept can be systematically applied in the RF front-end circuits, and it has helped with WBLNA reliability improvement.

A new synthesis methodology for reliable RF front-end Design

A low power and low cost WLAN/WiMAX RF front-end requires more advanced CMOS technologies whose transistor parameters degradation is becoming worse. Few published works has presented the reliability results for RF circuits. In order to fill this gap, we develop a new synthesis methodology for reliable RF front-end design using the design example of a reliable BLIXER. The first steps of our synthesis methodology is a transistor ageing simulation. Then, we calculate an estimation of the circuit performance and ageing using the circuit design equations and the total derivatives. Thus, we can find the required bias and sizing improving the circuit reliability. The simulation results of the typical circuit are coherent with the WLAN/WiMAX RF front-end specifications. Despite the integrated process variability and mismatch, we observe that 96.4 % of the simulation runs have Gain > 10.0 dB, and 92.1% of the simulation runs have NFmax< 5.0 dB. Moreover, the BLIXER ageing degradation is negligible according to the fitted Poisson distribution of the power consumption for 99.9% of confidence. Going further, we can say that the synthesis methodology proposed and developed for a RF front-end design can be exploited in different AMS/RF circuits and also generalized for a single bottom-up reliable-system design approach.

Current mode read-out circuit for InGaAs photodiode applications

Infrared focal plane arrays have many military, industrial, medical, and scientific applications that require high-resolution and high-performance read-out electronics. In applications involving InGaAs sensor arrays, data read-out can be carried out by circuits implemented with 0.35@mm CMOS technology. In this paper we propose a dynamically regulated cascode current mirror for pixel read-out. From simulation results, we expect this circuit to achieve a better trade-off between silicon area, signal-to-noise ratio, and output dynamic range than the trade-off that is currently achieved by current mode CMOS read-out circuits.

AMS and RF design for reliability methodology

The design for reliability concept is already in use on digital circuits, but not systematically in use on AMS or RF circuits. A reliable circuit design demands knowledge of the physical degradation and models to analyze the reliability in earlier stages. Also, it needs to be simple enough to be used on the redesign. In this work, we propose and validate an AMS and RF circuit design for reliability method. In order to investigate our method, we have designed a 5–3 NOR interpolative Digital Controlled Oscillator (DCO) near 1 GHz applications. This design example has presented 1.4% decrease of oscillation frequency, 0.2% decrease of phase noise for a 1 MHz off-set, and 2.1% decrease of power consumption after 10 years of degradation. According with the trends presented in Table I, we estimate that the fosc ageing degradation was improved of 13 % by applying the design for reliability method.

1.4 V and 300 nA UHF passive RFID voltage regulator

UHF passive RFID tags have become a natural option for long distance identification (few meters) as warehouse monitoring and vehicles control access. However, ultra-high frequency and long distance identification implies in very low received power. In order to achieve low power and reliability, a 1.4 V and 300 nA UHF passive RFID voltage regulator was designed in 130 nm CMOS. According to electric simulations of TT corner, we found a voltage regulation settling time smaller than 1 ms for a temperature coefficient of 220 ppm/°C. The voltage reference variability is μ= 712 mV and σ= 45 mV, estimated by a 1k points MC electric simulation. Finally, we found a PSRR smaller than -30 dB at 100 Hz, 27°C.

A synthesis methodology for AMS/RF circuit reliability: Application to a DCO design

Circuit ageing degradation is becoming worse in advanced technologies, while application fields like military, medical and energy demand more reliability. Thus, reliability is one of the most important challenges of the semiconductor industry [1]. In this work, we review the physical ageing phenomena, their simulation model, and how they can be avoided. Then, we propose a synthesis methodology composed of classical circuit optimization with the reliability analysis in earlier stages. Also, the variability of the integration process technology is taken into account. We compare a classical and a reliable designed digital controlled oscillator (DCO) in order to show a reduction of 16% in the oscillation frequency ageing degradation. In this way, the reliable design makes the circuit lifetime five times longer, if we fix the maximum frequency ageing degradation at 2.0%. Finally, we present the reliability as a design criterion, advantages and disadvantages of our methodology.

Monolithic integration of mutually injection-locked CMOS-MEMS oscillators for differential resonant sensing applications

Differential architectures based on two injection-locked MEMS oscillators are a promising technique for high-end resonant sensing applications since they enable environmental drift rejection and high sensitivity. But properly coupling two M/NEMS resonators together is challenging. In order to eliminate drift, the resonators must be fabricated very close to each other and to be as well-matched as possible. To this end, both resonators and the circuitry can be monolithically-integrated on a single chip. However this leads to parasitic coupling and feedthrough, which affect the performances. This paper explains how, block by block, our architecture and our chip are designed to minimize these spurious couplings. The improvements resulting from the optimization of the ASIC are illustrated by simulated and experimental results.

A high-Q tunable grounded negative inductor for small antennas and broadband metamaterials

This paper presents a broadband high-Q tunable negative inductor based on a gyrator topology. In order to reduce the risk of instability and to increase circuit bandwidth, simple inverters are used as transconductance amplifier. A complete stability analysis and careful circuit design details using SOI 180 nm technology are presented. Post-layout simulations results show a negative inductance variation from -24 nH to -13.7 nH. For a bandwidth from 10 MHz to 1 GHz, inductance value error remains under 12.5 %. Circuit power consumption is 16 mW; and area consumption is 120 μm by 84 μm.

A Unified Explanation of gm/ID-Based Noise Analysis

We present an unified explanation of the transconductance-to-drain current (gm/ID)-based noise analysis in this paper. We show that both thermal noise coefficient (γ) and device noise corner frequency (fco) are dependent on the gm/ID of a transistor. We derive expressions to demonstrate the relationship between the normalized noise power spectral density technique and the technique based on γ and fco. We conclude this letter with examples to demonstrate the practical implication of our study. Our results show that while both techniques discussed in this letter can be used to compute noise numerically, using γ and fco to separate thermal noise from flicker noise provides additional insight for optimizing noise.