Carsten Wulff

Analog Circuit Design in Nanoscale CMOS Technologies

As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic effects limiting matching accuracy, electromigration effects limiting conductor lifetime, leakage and mobility effects limiting device performance, and chip power dissipation limits driving individual circuits to be more energy-efficient. The lack of analog design and simulation tools available to address these problems has become the focus of a significant effort with the electronic design automation industry. Postlayout simulation tools are not useful during the design phase, while technology computer-aided design physical simulation tools are slow and not in common use by analog circuit designers. In the nanoscale era of analog CMOS design, an understanding of the physical factors affecting circuit reliability and performance, as well as methods of mitigating or overcoming them, is becoming increasingly important. The first part of the paper presents factors affecting device matching, including those relating to single devices as well as local and long-distance matching effects. Several reliability effects are discussed, including physical design limitations projected for future downscaling. In some cases, it may be helpful to exceed foundry-specified drain-source voltage limits by a few hundred millivolts. Models are presented for achieving this, which include the dependence on the shape of the output waveform. The condition Vsb > 0 is required for cascode circuit configurations. The role of other terminal voltages is discussed, as Vsb > 0 increases both hot and cold carrier damage effects in highly scaled devices. The second part of the paper focuses on trends in device characteristics and how they influence the design of nanoscale analog CMOS circuits. A number of circuit design techniques employed to address the major nonidealities of nanoscale CMOS technologies are discussed. Examples include techniques for establishing on-chip accurate and temperature-insensitive bias currents, digital calibration of analog circuits, and the design of regulator and high-voltage circuits. Achieving high energy efficiency in ICs capable of accommodating 109 devices is becoming critically important. This paper also presents a survey of the evolution of figure of merit for analog-to-digital converters.

Bootstrapped switch in low-voltage digital 90nm CMOS technology

The design of a bootstrapped switch in digital 90 nm CMOS technology, with 1.0 V supply voltage and 1 GHz sampling frequency for a 300 fF capacitive load is presented. Simulation results indicate that the switch has 10 bit linearity up to an input signal of 1.0 V peak-to-peak and frequency of 100MHz. The switch is intended for use in state-of-the-art data converters.

High speed, high gain OTA in a digital 90nm CMOS technology

The design of a high-speed, high gain OTA in a digital 90nm CMOS technology is presented. The OTA uses the gain enhancement technique outlined in (Bult and Geelen, 1990) to increase the DC gain. The amplifier is fully differential an utilizes fully differential gain enhancement OTAs. The frequency response shows that 70dB DC gain and a unity gain frequency of 2.5GHz is achieved. The OTA draws 20mA from a 1.2V power supply.

Design of A 7-bit, 200MS/s, 2mW pipelined ADC with switched open-loop amplifiers in a 65nm CMOS technology

We present the design of a 7-bit 200 MS/s pipelined ADC with switched open-loop amplifiers in a 65 nm CMOS technology. As a result of turning off the open-loop amplifiers during sampling we reduce the power dissipation by 23%. The ADC achieves a SNDR of 40 dB close to the Nyquist frequency, with a power dissipation of 2 mW, which results in a Walden FOM of 0.13 pJ/step and a Thermal FOM of 1.6 fJ/step.

0.8V 1GHz dynamic comparator in digital 90nm CMOS technology

The design of a 0.8V 1GHz dynamic comparator in digital 90nm CMOS technology is presented. The work shows that low voltage, low power and high speed analog circuits are feasible in nano-scale CMOS technologies. The dynamic comparator dissipates a maximum of 222/spl mu/W at 1 GHz clock frequency with 100fF capacitive load and 0.8 V supply voltage. This is lower than comparable results.

CBSC pipelined ADC with comparator preset, and comparator delay compensation

We present a differential comparator-based switched-capacitor (CBSC) pipelined ADC with comparator preset, and comparator delay compensation. Compensating for the comparator delay by digitally adjusting the comparator threshold improves the ADC resolution 23 times. The ADC is manufactured in a 90nm CMOS technology. The ADC core is 0.85mm × 0.35mm, with a 1.2V supply for the core and 1.8V for the input switches. The ADC has an effective number of bits (ENOB) of 7.05-bit, and a power dissipation of 8.5mW at 60MS/s.

On the energy efficiency of analog circuits in nanoscale CMOS technologies

Energy efficiency plays an important role in the design of high performance analog integrated circuits. With the introduction of nanoscale (sub-100 nm) CMOS technologies, it is becoming increasingly difficult to maintain the energy efficiency for high accuracy analog circuits. This paper derives figure-of-merit (FOM) limits for general analog circuits and discusses some design criteria that can be utilized to mitigate the impact of scaling on energy efficiency.

A Compiled 9-bit 20-MS/s 3.5-fJ/conv.step SAR ADC in 28-nm FDSOI for Bluetooth Low Energy Receivers

This paper presents a low-power 9-bit compiled successive-approximation register (SAR) analog-to-digital converter (ADC) for Bluetooth low energy receivers. The ADC is compiled from a SPICE netlist, a technology rule file, and an object definition file into a design rule check and layout versus schematic clean layout and schematic in 28-nm FDSOI. The compiled SAR ADC reduces the design time necessary to port to a new technology, and to demonstrate technology porting the same SAR ADC architecture is compiled in 28-nm FDSOI with Input/Output (IO) transistors. This paper also includes a comparator clock generation loop that uses the bottom plate of the capacitive digital-to-analog converter. The proposed compiled core transistor SAR ADC achieves the state-of-the-art Figure of Merit (FoM) of 2.7 fJ/conv.step at 2 MS/s, and 3.5 fJ/conv.step at 20 MS/s with an area of 0.00312 mm2.

Noise transfer functions and loop filters especially suited for noise-shaping SAR ADCs

Oversampling and noise-shaping have in recent years been introduced to SAR ADCs to improve the conversion accuracy. Similar to delta-sigma ADCs, this is done by means of a feedback loop containing a loop filter. In this paper, the high-level design of this loop filter is discussed, and important differences to classical delta-sigma loop filter design are pointed out. Among others, it is found that the poles of the noise transfer function, and not only the zeros, play a significant role on the conversion accuracy. Based on this, a new loop filter topology with four poles and two zeros is proposed and compared to existing loop filters. This reveals that the proposed loop filter can yield more energy-efficient noise-shaping SAR ADCs than the ones seen in the literature today.

A compiled 3.5fJ/conv.step 9b 20MS/s SAR ADC for wireless applications in 28nm FDSOI

A low power 9-bit compiled SAR ADC is presented. The ADC is compiled from a netlist, rule file, and object definition file into a DRC/LVS clean layout and schematic in 28nm FDSOI. The presented ADC also includes a comparator clock generation loop that use the bottom plate of the CDAC. The proposed compiled ADC achieves a FoM of 2.7fJ/conv.step at 2MS/s, and 3.5fJ/conv.step at 20MS/s with an area of 0.00312mm2. To demonstrate process independence the same SAR architecture is compiled in 28nm FDSOI with IO transistors.