Trond Ytterdal

Conducting laboratory experiments over the Internet

We report on an interactive on-line laboratory for remote education called Automated Internet Measurement Laboratory (AIM-Lab), which utilizes the Internet and the World Wide Web. AIM-Lab allows efficient use of laboratory equipment in both regular and laboratory courses, especially in a distance-learning environment. Our approach is based on newly developed software packages and commercial measurement equipment. As an example, we describe an application of remote experiments on semiconductor device characterization, which can be freely accessed on the Web.

Analog Circuit Design in Nanoscale CMOS Technologies

As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic effects limiting matching accuracy, electromigration effects limiting conductor lifetime, leakage and mobility effects limiting device performance, and chip power dissipation limits driving individual circuits to be more energy-efficient. The lack of analog design and simulation tools available to address these problems has become the focus of a significant effort with the electronic design automation industry. Postlayout simulation tools are not useful during the design phase, while technology computer-aided design physical simulation tools are slow and not in common use by analog circuit designers. In the nanoscale era of analog CMOS design, an understanding of the physical factors affecting circuit reliability and performance, as well as methods of mitigating or overcoming them, is becoming increasingly important. The first part of the paper presents factors affecting device matching, including those relating to single devices as well as local and long-distance matching effects. Several reliability effects are discussed, including physical design limitations projected for future downscaling. In some cases, it may be helpful to exceed foundry-specified drain-source voltage limits by a few hundred millivolts. Models are presented for achieving this, which include the dependence on the shape of the output waveform. The condition Vsb > 0 is required for cascode circuit configurations. The role of other terminal voltages is discussed, as Vsb > 0 increases both hot and cold carrier damage effects in highly scaled devices. The second part of the paper focuses on trends in device characteristics and how they influence the design of nanoscale analog CMOS circuits. A number of circuit design techniques employed to address the major nonidealities of nanoscale CMOS technologies are discussed. Examples include techniques for establishing on-chip accurate and temperature-insensitive bias currents, digital calibration of analog circuits, and the design of regulator and high-voltage circuits. Achieving high energy efficiency in ICs capable of accommodating 109 devices is becoming critically important. This paper also presents a survey of the evolution of figure of merit for analog-to-digital converters.

SPICE Models for Amorphous Silicon and Polysilicon Thin Film Transistors

We describe physically based analytical models for n-channel amorphous silicon thin film transistors and for n- and p-channel polysilicon thin film transistors. The models cover all regimes of transistor operation: leakage, subthreshold, above-threshold conduction, and the kink regime in polysilicon thin film transistors. The models contain a minimum number of parameters which are easily extracted and can be readily related to the structural and material properties of the thin film transistors. The models have been verified for a large number of devices to scale properly with device geometry.

A short-channel DC SPICE model for polysilicon thin-film transistors including temperature effects

A semi-empirical analytical model for the DC characteristics of both n- and p-channel polysilicon thin-film transistors is described. The model is suitable for implementation in a SPICE circuit simulator. Our semi-empirical approach results in a physically based model with a minimum of parameters, which are readily related to the device structure and fabrication process. The intrinsic DC model describes all four regimes of operation: leakage, subthreshold, above threshold, and kink. The effects of temperature and channel length are also included in the short-channel model.

Device Modeling for Analog and RF CMOS Circuit Design: Ytterdal/Device

Preface. MOSFET Device Physics and Operation. MOSFET Fabrication. RF Modeling. Noise Modeling. Proper Modeling for Accurate Distortion Analysis. The BSIM4 MOSFET Model. The EKV Model. Other MOSFET Models. Bipolar Transistors in CMOS Technologies. Modeling of Passive Devices. Effects and Modeling of Process Variation and Device Mismatch. Quality Assurance of MOSFET Models. Index.

Unified MOSFET model

Abstract We present a basic analytical MOSFET model which describes both the below and above threshold regimes of device operation. The description is based on a charge control model which uses one unified expression for the effective differential channel capacitance. The model also accounts for series drain and source resistances, velocity saturation in the channel, finite output conductance in the saturation regime, and for the threshold voltage shift due to drain bias induced lowering of the injection barrier between the source and the channel (DIBL). The model parameters, such as the effective channel mobility, the saturation velocity, the source and drain resistances, etc. are extractable from experimental data. The model has been incorporated into our simulator, AIM-Spice. We apply the characterization procedure based on this model to a MOSFET with a quarter micron gate length and obtain excellent agreement with experimental data.

Enhanced GaAs MESFET CAD model for a wide range of temperatures

We describe a new and enhanced GaAs MESFET model suitable for implementation in computer aided design (CAD) software packages such as, for example, SPICE. The model accurately reproduces both above-threshold and subthreshold characteristics of GaAs MESFETs in a wide temperature range, from 77 K to 350/spl deg/C. The current-voltage characteristics are described by a single continuous, analytical expression for all regimes of operation. The physics-based model includes effects such as velocity saturation in the channel, drain induced barrier lowering, finite output conductance in saturation, bias dependent series source and drain resistances, effects of bulk charge, bias dependent average low-field mobility, frequency dependent output conductance, backgating and sidegating, and temperature dependent model parameters. The output resistance and the transconductance are also accurately reproduced, making the model suitable for analog CAD. >

Current-Mode Capacitive Sensor Interface Circuit With Single-Ended to Differential Output Capability

This paper presents a current-mode interface circuit for capacitive sensors, with the main features being its ability to produce a differential output from a single-ended sensor (using a fixed reference capacitor) and its simplicity in realization. These advantages make it a potential candidate for applications where differential sensors are not available and where a simple design is required. The principle is, however, easily applicable to differential sensors as well. The interface concept can be realized in different ways; however, to present a proof of concept on silicon, a prototype has been fabricated and tested in a commercially available 0.8-mum CMOS process. The circuit has been designed using common analog building blocks such as a fully differential operational transconductance amplifier (OTA), a high-output-resistance wide-swing current source, and a single clock phase. The estimated linearity error was 0.2% relative to full-scale swing with a simple two-point calibration. The circuit consumes 145 muA from a 5-V power supply.

Enhancement of Schottky barrier height in heterodimensional metal-semiconductor contacts

We report on the measurements of the heterodimensional Schottky barrier height in two-dimensional metal-semiconductor field effect transistors (2D MESFETs). Our experimental data indicate approximately 0.1 eV greater barrier height compared to conventional metal-semiconductor contacts of the same materials. The enhancement is explained in terms of two effects—quantization of energy levels of the carriers in the quantum well and broadening of the corresponding wave functions. The increased barrier height leads to a substantial reduction of the gate leakage current in 2D MESFETs.

Narrow channel 2-D MESFET for low power electronics

A 2-D MESFET utilizing sidewall Schottky contacts on either side of a very narrow 2-d electron gas channel is described. Record transconductance of 295 and 130 mS/mm have been achieved at room temperature in 1.0 and 0.5 micron wide devices, respectively. We also present accurate 2-D MESFET current-voltage and capacitance-voltage models. These models have been implemented into AIM-Spice which was used to simulate DCFL inverter and ring oscillator circuits. The ring oscillator simulations predict a power-delay product of less than 0.1 fJ/gate at room temperature, suggesting that the 2-D MESFET may be useful for ultra low power electronics applications. >