F. Colodro

New Continuous-Time Multibit Sigma–Delta Modulators With Low Sensitivity to Clock Jitter

In this paper, new continuous-time sigma-delta modulators (SDMs) are proposed where the output of a multibit (MB) quantizer is digitally converted to a single-bit pulsewidth-modulated (PWM) signal at a higher rate. The PWM signal is then fed back to the input through a finite-impulse-response digital-to-analog converter (DAC). The proposed modulators are shown to be less sensitive to clock jitter than their equivalent MB SDM, while their amplifiers have similar speed and power requirements. Furthermore, the proposed modulators do not require dynamic-element-matching techniques in the feedback path because a mismatch of the unit elements in the MB DAC does not produce distortion nor increases the noise floor in the signal band.

Continuous-Time Sigma–Delta Modulator With an Embedded Pulsewidth Modulation

A new Continuous-Time (CT) sigma-delta modulator (SDM) based on the well-known asynchronous SDM is proposed in this paper. To this end, the flash quantizer and the digital-to-analog converter (DAC) in a multibit (MB) CT-SDM clocked at a rate fmax are replaced by a single-bit (SB) comparator with hysteresis clocked at a higher rate fs and a SB-DAC, respectively. By proper selection of the hysteresis in the comparator and the ratio F = fs/fmax, the performances of both modulators are shown to be equivalent. The comparator with hysteresis and the loop filter produce, in the modulator output, a limit cycle of frequency /max which is modulated by the input signal. Therefore, the modulator output can be considered to be a pulsewidth (PW) modulated signal with a frequency approximately equal to /max, and the proposed modulator is called a PW-SDM. Despite the high sampling rate of the comparator output, the integrators and the SB-DAC of the proposed modulator have the same speed requirements as those of the equivalent conventional MB-SDM. On the other hand, in the proposed modulator there are not MB (analog-to-digital or digital-to-analog) converters. Therefore, for a given set of specifications, the proposed PW-SDM is expected to consume less power and area than its equivalent conventional MB modulator.

Digital noise-shaping of residues in dual-quantization sigma-delta modulators

A new dual-quantization Sigma-Delta modulator is proposed in this paper where the coarse-quantizer output, obtained from the fine-quantizer output by means of a digital noise-shaping coder, is fed back to the input of the first integrator by means of a p-bit digital-to-analog converter (DAC) (typically, p=1). To avoid the truncation error inserted into the first integrator to propagate to the rest of integrators, the residue of the digital coder is first integrated and then fed to the second integrator through an additional multibit DAC. Unlike other dual-quantization architectures, the proposed one allows to obtain a large signal-to-noise plus distortion ratio by using aggressive noise transfer functions, like in conventional multibit modulators. Mismatch effects on performances are carefully analyzed. It will be shown that more than one digital coder can be included in the architecture in order to reduce the number of bits of the additional DAC. Simulation results are presented which support the theoretical analysis.

Two digital circuits for a fully parallel stochastic neural network

This paper presents two digital circuits that allow the implementation of a fully parallel stochastic Hopfield neural network (SHNN). In a parallel SHNN with n neurons, the n*n stochastic signals s (ij) pulse with probability which are proportional to the synapse inputs, are simultaneously available. The proposed circuits calculate the summation of the stochastic input pulses to neuron i(F(i)=Sigma(j) s(ij)). The resulting network achieves considerable speed up with respect to the previous network.

Multirate single-bit /spl Sigma//spl Delta/ modulators

It has been shown that a multibit /spl Sigma//spl Delta/ modulator can be built replacing the multibit quantizer in the forward path by a single-bit one, operating at a higher frequency, by an increase in the oversampling ratio of the last integrators of the loop. An improved topology is proposed here which obtains similar performances with single-bit feedback, overcoming drawbacks inherent to high resolution digital to analog converters.

A fuzzy-logic controller with on-chip learning, employing stochastic logic

There is an increasing interest in the development of efficient fuzzy controller hardware, able to cope with the requirements of real-time systems. Several fuzzy-logic chips have been proposed using both analog and digital techniques. This paper presents a hardware implementation of a digital fuzzy controller that uses stochastic logic to implement the arithmetic functions involved in the defuzzification and learning processes. Stochastic logic systems use binary random signals whose average can be viewed as an analog value in the range [0,1]. Using stochastic logic has a number of advantages over other analog and digital implementations, such as multiplication using a simple AND gate. Stochastic logic has been successfully applied to different fields including neural processing. A proper selection of the different parts of the controller and the use of stochastic logic leads to a simple digital architecture with a short response time (less than 21 /spl mu/s for a 7 bit stochastic precision and a 12 MHz system clock). A feature of the proposed controller is its learning capability, obtained by adjusting the position of the output singletons. Presently, a prototype of the controller is being designed using a 1.5 /spl mu/m CMOS technology.<<ETX>>

Frequency-to-digital conversion based on a sampled Phase-Locked Loop

A new Frequency-to-Digital (F2D) converter based on a Phase-Locked Loop (PLL) is presented in this paper where the square wave at the output of a Voltage Controlled Oscillator (which is also the PLL output) is sampled and fed back to one of the Phase-Frequency Detector inputs. This sampled output is digitally processed and the information carried in its frequency is converted to a digital signal by means of a digital differentiator. Theoretical analyses and system-level simulations show that the errors produced by the sampling are shaped by a high-order transfer function in the same way as quantization errors are shaped in a Sigma-Delta Modulator. In addition, transistor-level simulations show a low sensitivity to non-linear circuit errors. The proposed F2D converter is suitable for integration in modern nanometer CMOS technologies, and can be used as an FM demodulator.

Continuous-Time Sigma–Delta Modulator With a Fast Tracking Quantizer and Reduced Number of Comparators

Using a tracking analog-to-digital converter as the quantizer of a sigma-delta modulator (SDM) has been shown to be an efficient method of reducing the number of comparators. In this paper, a new continuous-time (CT) SDM is proposed where a large reduction in the number of comparators is obtained by clocking the quantizer tracking loop at a high frequency rate. For a given example, the number of bits of the quantizer is shown to be reduced from five in the original multibit modulator to only one in a quantizer with tracking sampled at three times the original sampling frequency. In addition, the output of the tracking quantizer can be downsampled so that the modulator output has the same resolution and sampling rate as the original modulator. In this way, the design of the digital-to-analog converters in the feedback loop and the decimator filter at the modulator output are not penalized. Furthermore, the digital integrator of the tracking loop can be removed by taking profit of the last CT integrator in the forward path. Finally, the signal component in the forward path can be attenuated by adding a direct path from the modulator input to the last integrator input. As a result, the output swing of the integrators is reduced, improving the linearity of the whole modulator. The new modulators are analyzed and extensive theoretical and simulation results are provided.

Time-interleaved multirate sigma-delta modulators

A new strategy for the implementation of multirate sigma-delta modulators (SDM) is proposed in this paper. In multirate SDM, the first integrator is clocked at a rate lower than the rest of the integrators in the forward path. In the new architecture, each integrator clocked at the high rate is replaced by two parallel integrators operating in interleaving mode and clocked at the same low rate as the first one. The new architecture has several nice features. Firstly, all integrators operate at the same low rate, which simplifies the clock generation circuit. Secondly, the delayed cross-paths in time-interleaved (TI) SDM, which are difficult to implement, are not present in the proposed architecture. Thirdly, the high-rate sample and hold (S and H) circuit at the input of TI-SDM is replaced by a low-rate one in the proposed modulator. Finally, the first integrator is clocked at low rate and is implemented as a single-path module. Accordingly, the modulator is simplified in silicon area and complexity. Furthermore, the architecture is very robust to mismatch between paths.

Towards a fully parallel stochastic Hopfield neural network

The authors present two digital circuits to implement a fully parallel stochastic Hopfield neural network (SHNN). In a parallel SHNN all the n /spl times/ n stochastic signals s/sub ij/ that pulse with probability proportional to the synapse inputs are simultaneously available. The proposed circuits calculate the function F/sub i/ that accumulates the number of positive (negative) stochastic input pulses to neuron i.<<ETX>>