Cathy Wang

Evaluation of a new metrology technique to support the needs of accuracy, precision, speed, and sophistication in near-future lithography

A new metrology technique is being evaluated to address the need for accuracy, precision, speed and sophistication in metrology in near-future lithography. Attention must be paid to these stringent requirements as the current metrology capabilities may not be sufficient to support these near future needs. Sub-nanometer requirements in accuracy and precision along with the demand for increase in sampling triggers the need for such evaluation. This is a continuation of the work published at SPIE Asia conference, 2008. In this technical presentation the authors would like to continue on reporting the newest results from this evaluation of such technology, a new scatterometry based platform under development at ASML, which has the potential to support the future needs. Extensive data collection and tests are ongoing for both CD and overlay. Previous data showed overlay performance on production layers [1] that meet 22 nm node requirements. The new data discussed in this presentation is from further investigation on more process robust overlay targets and smaller target designs. Initial CD evaluation data is also discussed.

Evaluation of a novel ultra small target technology supporting on- product overlay measurements

Reducing the size of metrology targets is essential for in-die overlay metrology in advanced semiconductor manufacturing. In this paper, μ-diffraction-based overlay (μDBO) measurements with a YieldStar metrology tool are presented for target-sizes down to 10 × 10 μm2. The μDBO technology enables selection of only the diffraction efficiency information from the grating by efficiently separating it from product structure reflections. Therefore, μDBO targets -even when located adjacent to product environment- give excellent correlation with 40 × 160 μm2 reference targets. Although significantly smaller than standard scribe-line targets, they can achieve total-measurement-uncertainty values of below 0.5 nm on a wide range of product layers. This shows that the new μDBO technique allows for accurate metrology on ultra small in-die targets, while retaining the excellent TMU performance of diffraction-based overlay metrology.

On-product overlay enhancement using advanced litho-cluster control based on integrated metrology, ultra-small DBO targets and novel corrections

Aggressive on-product overlay requirements in advanced nodes are setting a superior challenge for the semiconductor industry. This forces the industry to look beyond the traditional way-of-working and invest in several new technologies. Integrated metrology2, in-chip overlay control, advanced sampling and process correction-mechanism (using the highest order of correction possible with scanner interface today), are a few of such technologies considered in this publication.

A sophisticated metrology solution for advanced lithography: addressing the most stringent needs of today as well as future lithography

Advanced lithography is becoming increasingly demanding when speed and sophistication in communication between litho and metrology (feedback control) are most crucial. Overall requirements are so extreme that all measures must be taken in order to meet them. This is directly driving the metrology resolution, precision and matching needs in to deep sub-nanometer level [4]. Keeping the above in mind, a new scatterometry-based platform is under development at ASML. Authors have already published results of a thorough investigation of this promising new metrology technique which showed excellent results on resolution, precision and matching for overlay, as well as basic and advanced capabilities for CD [1], [2], [3]. In this technical presentation the authors will report the newest results from this ASML platform. This new work was divided in two sections: monitor wafer applications (scanner control - overlay, CD and focus) and product wafer applications.

A paradigm shift in scatterometry-based metrology solution addressing the most stringent needs of today as well as future lithography

Advanced lithography is becoming increasingly demanding when speed and sophistication in communication between litho and metrology (feedback control) are most crucial. Overall requirements are so extreme that all measures must be taken in order to meet them. This is directly driving the metrology resolution, precision and matching needs in to deep sub-nanometer level as well as driving the need for higher sampling (throughput). Keeping the above in mind, a new scatterometry-based platform (called YieldStar) is under development at ASML. Authors have already published results of a thorough investigation of this promising new metrology technique which showed excellent results on resolution, precision and matching for overlay, as well as basic and advanced capabilities for CD. In this technical presentation the authors will report the newest results taken from YieldStar. This new work is divided in two sections: monitor wafer applications and product wafer applications. Under the monitor wafer application: overlay, CD and focus applications will be discussed for scanner and track hotplate control. Under the product wafer application: first results from integrated metrology will be reported followed by poly layer and 3D CD reconstruction results from hole layers as well as overlay-results from small (30x60um), process-robust overlay targets are reported.

A comprehensive look at a new metrology technique to support the needs of lithography performance in near future

Need for accuracy, precision, speed and sophistication in metrology has increased tremendously over the past few years. Lithography performance will increasingly depend on post patterning metrology and this dependency will be heavily accelerated by technology shrinkage. These requirements will soon become so stringent that the current metrology capabilities may not be sufficient to support these near future needs. Accuracy and precision requirements approaching well into sub-nanometer range while the demand for increase in sampling also continues, triggering the need for a new technology in this area. In this technical presentation the authors would like to evaluate such technology that has the potential to support the future needs. Extensive data collection and tests are ongoing for both CD and overlay. Data on first order diffraction based overlay shows unprecedented measurement precision. The levels of precision are so low that for evaluation special methods has been developed and tested. In this paper overlay measurement method and data will be discussed, as well as applicability for future nodes and novel lithography techniques. CD data will be reported in the future technical publications.

Litho process control via optimum metrology sampling while providing cycle time reduction and faster metrology-to-litho turn around time

In keeping up with the tightening overall budget in lithography, metrology requirements have reached a deep subnanometer level [1]. This drives the need for clean metrology (resolution and precision). Results have been published of a thorough investigation of a scatterometry-based platform from ASML [7], showing promising results on resolution, precision, and tool matching for overlay, CD and focus [2 - 6]. But overall requirements are so extreme that all measures must be taken in order to meet them. In light of this, in addition to above-mentioned need for resolution and precision, the speed and sophistication in communication between litho and metrology (feedback control) are also becoming increasingly crucial. An effective sampling strategy for metrology plays a big role in order to achieve this. This study discusses results from above mentioned scatterometry-based platform in light of sampling optimization. For overlay, various sampling schemes (dense / sparse combinations as well as inter and intra field schemes) were used on many production lots. The effectiveness of such sample schemes were studied to reveal an ideal sampling scheme that can result in 0.5nm to 1nm gain in overlay control (compare to todays practice). Moreover, cycle time contribution of metrology (at litho) in overall cycle time of a full process flow was investigated and quantified with the concept of integrated metrology. Results indicate a cycle time reduction per layer (if an integrated concept is used) of 3 to 5 hours, which can easily add up to several days of total cycle time reduction for a fab.

Holistic approach using accuracy of diffraction-based integrated metrology to improve on-product performance, reduce cycle time, and cost at litho

High-end semiconductor lithography requirements for CD, focus and overlay control drive the need for diffraction-based metrology1,2,3,4 and integrated metrology5. In the advanced nodes, more complex lithography techniques (such as multiple patterning), use of multi-layer overlay measurements in process control, advanced device designs (such as advanced FinFET), as well as advanced materials (like hardmasks) are introduced. These pose new challenges for lithometro cycle time, cost, process control and metrology accuracy. In this publication a holistic approach is taken to face these challenges via a novel target design, a brand new implementation of multi-layer overlay measurement capability in diffraction-based mode and integrated metrology.

A holistic scanner matching solution for productivity enhancement in a Giga fab

In this work, we propose a new technique for comprehensive scanner matching to fundamentally improve scanner productivity in a Giga fab. The proposal covers matching solutions for both CD and overlay fingerprints among scanners. CD matching strategy has three main components. The first part is to apply modelbased scanner tuning for scanner optics matching. The second part is to apply hotplate-tuning mechanism for within-wafer CD uniformity improvement. The third part is to achieve focal plane control with a novel focus metrology method. Overlay control and matching are achieved with periodic inter-field and intra-field high order process correction with respect to the chosen baseline of overlay fingerprint for each scanner. Together with the existent inline automatic process control infrastructure, which suppresses the residual process-induced CD and overlay variations, a holistic scanner matching solution can be implemented in the fab for productivity and yield enhancements. Convincing proof data is provided in this paper to demonstrate the feasibility of our approach.

Throughput improvement from routing reduction by using CPE (correction per exposure)

The etch loading effect from wafer center to wafer edge results in worse Bit-line Contact layer (CB) to Gate Conductor layer (GC) overlay alignment performance at the wafer edge which directly impacts device yield. One workaround for this is to introduce additional image shifts during exposure at the edge of the wafer however this will reduce throughput due to the extra time required for wafer measurement (additional leveling scans) and extra exposure time (additional image). We demonstrate a new method which can avoid this overhead using Correction Per Exposure (CPE). We are proposing to use CPE with manually generated overlay corrections. In this way, we are achieving the necessary wafer-edge overlay compensation, and there is no throughput-loss because there is no extra-routing.