Jacky Huang

Impact of source/drain Si1-yCy stressors on silicon-on-insulator N-type metal-oxide-semiconductor field-effect transistors

The stress field in the channel of a silicon-on-insulator (SOI) N-type metal–oxide–semiconductor field-effect transistor (NMOSFET) with silicon–carbon alloy source and drain stressors was evaluated. The physical origin of the stress components in the transistor channel region was explained. The magnitude and distribution of the strain components, and their dependence on device design parameters such as the spacing between the silicon–carbon alloy stressors, the carbon mole fraction in the stressors and stressor recessed depth and raised height were investigated. The reduction in the stressor spacing or increase in the carbon mole fraction of the stressors and the stressor recessed depth and raised height increase the magnitude of the vertical compressive stress and the lateral tensile stress in the portion of the channel region where the inversion charge exists. This is beneficial for improving the electron mobility in NMOSFETs. A simple guiding principle for an optimum combination of the above-mentioned device design parameters and the trade-off between performance and junction leakage current degradation is discussed in this paper.

Study of the impact of charge-neutrality level (CNL) of grain boundary interface trap on device variability and P/E cycling endurance of 3D NAND flash memory

Poly-Si thin-film transistor (TFT) is the key building element for high-density 3D NAND Flash memory. Random grain boundary (GB) location and interface traps (Dit) density have been shown as the major root cause of variability [1]. However, with CNL pinned at midgap our previous model cannot adequately address experimental results - especially the cause of very low Vt TFT devices. In this work we point out that to accurately model the TFT device, CNL should not be restricted at the mid-gap only, as in the conventional assumption for Si/SiO2 interface trap, but should be randomly distributed inside the bandgap for GB trap. This makes donor-type Dit active besides the acceptor-type Dit. Simulation including the random CNL can well explain the very low-Vt devices and gives better TFT variability model. Furthermore, GB trap CNL plays an important role in governing the device subthreshold behavior during PE cycling for 3D NAND Flash.

Impact of channel width and dummy length on performance enhancement in p-type metal oxide semiconductor field effect transistor with a silicon-germanium alloy stressor

The stress distribution in the Si channel regions of silicon-germanium (SiGe) source/drain p-type metal oxide semiconductor field effect transistor of various widths and dummy lengths was studied using ANSYS simulations. The drain current enhancement is dominated by the compressive stress along the transport direction. Stress perpendicular to the channel was found to have the least effect on the drain current in wide-width devices. However, this stress component cannot be neglected in narrower devices. The tensile stress along the vertical direction contributes to the drain current enhancement in wide devices but can be neglected when the width is very small. The impact of channel width and dummy length effects on improvements in device performance such as the drive current gain was also analyzed.

Carrier backscattering characteristics of nanoscale strained complementary metal-oxide-semiconductor devices featuring the optimal stress engineering

The authors present stress distribution simulation characterization of the three-dimensional boundary effects and show how these effects can impact the achievable transistor performance gain. The high-performance complementary metal-oxide-semiconductor (CMOS) device has been achieved by stressors such as contact etch stop layer (CESL) and SiGe S/D and optimal geometric structure design. The biaxial-like stress distribution resulting from symmetry structure and uniaxial-like stress distribution resulting from asymmetry structure seems to be promising when considering drive current enhancement, the ballistic efficiency, and carrier injection velocity for CMOS devices. The comprehensive study helps the future nanoscale CMOS device design and demonstrates that the stress enhancement factors remain valid for future technology.

Impact of width effect on performance enhancement in NMOSFETs with silicon-carbon alloy stressor and stress CESL

We simulated stress components in three directions in the Si channel of NMOSFETs with SiC alloy S/D stressor and tensile CESL in this study. The resulting saturation drain current enhancement was analyzed. Tensile stress along the transport direction was found to dominate mobility enhancement. Stress along the width direction was found to affect drain current the least. However, for NMOSFETs, the compressive stress along vertical direction perpendicular to the gate oxide the makes considerable contribution to mobility enhancement and can not be neglected. To obtain the new mobility model for this study, we extended a simple model for strain effect in Si band, to include both shear strain and the quantum confinement effect in the inversion layer of NMOSFETs.

3D Simulations of Width Effect on Performance in NMOSFETs with SiC S/D Stressors and CSEL Linear

Stress distribution in the Si channel regions of SiC source/drain NMOSFETs with various widths is studied by 3D simulations. The impact of width on performance improvement is analyzed.