Cedric Walravens

Design of a low-energy data processing architecture for WSN nodes

Wireless sensor nodes require low-energy components given their limited energy supply from batteries or scavenging. Currently, they are designed around off-the-shelf low-power microcontrollers for on-the-node processing. However, by employing more appropriate hardware, the energy consumption can be significantly reduced. This paper identifies that many WSN applications employ algorithms which can be solved by using parallel prefix-sums. Therefore, an alternative architecture is proposed to calculated them energy-efficiently. It consists of several parallel processing elements (PEs) structured as a folded tree. Profiling SystemC models of the design with ActivaSC helps to improve data-locality. Measurements of the fabricated chip confirm an improvement of 10-20x in terms of energy as compared with traditional MCUs found in sensor nodes.

Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes

Radio communication exhibits the highest energy consumption in wireless sensor nodes. Given their limited energy supply from batteries or scavenging, these nodes must trade data communication for on-the-node computation. Currently, they are designed around off-the-shelf low-power microcontrollers. But by employing a more appropriate processing element, the energy consumption can be significantly reduced. This paper describes the design and implementation of the newly proposed folded-tree architecture for on-the-node data processing in wireless sensor networks, using parallel prefix operations and data locality in hardware. Measurements of the silicon implementation show an improvement of 10-20× in terms of energy as compared to traditional modern micro-controllers found in sensor nodes.

ActivaSC: a highly efficient and non-intrusive extension for activity-based analysis of SystemC models

Todays highly integrated system-on-chips (SoC) demand innovative architectural modeling means to cope with their energy constraints. In this context, SystemC has become a well-established simulation tool for transaction level modeling (TLM) in the integrated electronics industry but it lacks the support for power modeling. This paper introduces ActivaSC, a flexible, fast, transparent and non-intrusive extension to the SystemC class library which allows capturing the activity information of a digital system being modeled. This information can then be post-processed to estimate power consumption. ActivaSC avoids time consuming design iterations as designers can assess architectural design trade-offs based on system activity early in the design flow. ActivaSC does not require any code alterations nor a specific API, so that it can be used with any modeling style. Finally, several benchmark tests illustrate the superior efficiency of ActivaSC. A speed-up of up to 75% in terms of elaboration overhead and 20% in terms of simulation overhead is realized with respect to prior art.

Breaking up gigabit ethernet's VoIP bottlenecks

Gigabit Ethernet is a popular broadband technology for good reason. It not only can transfer large amounts of data through a large network at high speeds, but it also is a mature technology with an appealing performance to cost-of-ownership ratio. Unfortunately, though, gigabit Ethernet suffers a performance drop when it is handling traffic with small packets: it tends to lose them. This is a serious problem because small packets have become important in many real-time applications - in voice over Internet protocol (VoIP), for example, which carries voice conversations over the Internet. We have studied high-rate, small-packet traffic in an Ethernet controller, as implemented in an Intel e1000 network interface card (NIC) Linux driver, which is widely used in high-end systems and servers. We have also evaluated the performance boost provided by the receive descriptor recycling (RDR) technique.

Receive descriptor recycling for small packet high speed Ethernet traffic

This paper presents the concept of receive descriptor recycling to significantly reduce the performance drop associated with small packet Gigabit Ethernet traffic. Since limits and trade-offs are inherent when optimising for small packet traffic, all important aspects in this context are covered. Low-level measurements were performed at the CERN LHCb online data acquisition (DAQ) system, which is to a large extend made up of commodity equipment. Results gathered show the Ethernet controller (network interface card, NIC) driver currently is the major bottleneck, preventing the system from reaching maximal Gigabit Ethernet performance. Receive descriptor recycling is implemented under Linux for Intels e1000 NIC driver, and is shown to successfully remedy the driver inefficiency

RFID, Where are they?

This paper gives an overview of RFID technology. RFID systems are described in general and a few example cases are given. After that the paper mainly focuses on the hardware requirements for RFIDs. Also Real Time Locationing Systems (RTLS) are discussed. This gives the title of the paper a double meaning: ‘what is the state of the art in RFID’ but also what is the available technology to come to locationing capable RFID systems. The paper gives an overview of the design challenges of different RFID systems. Also possible circuit solutions and directions are addressed.

Leuven Student Branch and SSCS Chapters Organize 2nd SSCS-Benelux Microelectronics Symposium

The second annual Microelectronics Symposium at K.U.Leuven, organized by the IEEE-Leuven Student Branch and SSCS-Benelux chapters in March, 2008 with the help of On Semiconductor (formerly AMIS) and NXP, featured five invited talks on how industry and research institutions cope with constraints such as cost, energy consumption, and silicon area to advance the current state-of-the-art.