César Augusto Prior

Behavioral modeling of continuous-time ΣΔ modulators in matlab/simulink

In this paper, a behavioral model of Continuous-Time (CT) Sigma-Delta Modulators (ΣΔMs) is presented. The non-idealities of the ΣΔM such as operational amplifiers finite parameters (DC gain, slew-rate, voltage saturation and unity gain frequency), excess loop delay, clock jitter and quantizer offset are modeled in Matlab/Simulink environment providing accurate time-based simulations. For demonstration purposes, a 3rd order single bit CT ΣΔM topology with Non-Return to Zero (NRZ) and another one with Switched-Capacitor Resistor (SCR) DAC feedback are simulated and have their performance degradation due to non-idealities analyzed. The effects of the non-idealities are clearly seen when compared to the ideal modulator. Also, key design specifications for the functional building blocks could be derived from simulations with the proposed models.

Design of an integrated low power high CMRR instrumentation amplifier for biomedical applications

This paper presents the design of a low-power high-CMRR CMOS instrumentation amplifier (IA) aimed for biomedical applications. The amplifier fundamentals were initially presented followed by its main building blocks. Simulation and experimental results were presented and discussed. The IA circuit was designed in AMIS 1.5 µm technology and manufactured through the MOSIS Service. The measured gain,CMRR and power consumption were 65dB, 120dB and 100uW respectively.

A switched current sigma delta modulator using a low distortion feedfoward topology

Implementation of feedforward paths for low-distortion topologies on switched capacitor sigma-delta (SC-SD) modulators was successfully reported elsewhere [13]. In this paper we propose the use of a similar low distortion topology on an implementation of a switched current sigma-delta (SI-SD) modulator. The objective is a reduction of harmonic distortion observed in implementations with simple integrator cells. In this approach, one of the main SI cell drawbacks, the harmonic distortion due to conductance variation, can be reduced by alleviating the signal in the integrators path. In this approach, the integrators ideally process only noise. Relaxing requirements of integrators allows simpler and faster switched-current integrator circuits. The feedforward SI-SD modulator was designed in XFAB CMOS 0.6µm technology. Simulated results points to a reduction of harmonic distortion from 2% in a classical 2nd order feedback topology to 0.2% in the feed forward design. It also provides a reduction of 30% in the silicon area, and higher sampling frequency.

Instrumentation Amplifier using Robust Rail-to-Rail Operational Amplifiers with gm Control

An instrumentation amplifier based on constant gm, rail-to-rail transconductance amplifiers is presented. The circuit was designed to 0.5 mum AMIS CS CMOS technology. Simulation results show that a -3 dB bandwidth about 190 kHz could be obtained. Operating with a 3 V supply and its dc gain set to 66 dB, the amplifier has a power consumption of 110 muW, and a CMRR higher than 140 dB.

System-level Design of Single-bit Sigma-Delta Modulators Based on MSA and SNR Data Graphics

This paper presents a more comprehensive approach for the design of single-bit single-loop sigma-delta modulators, either in continuous or discrete-time domain. The approach is based on SNR and MSA data graphics generated for second-, third- and fourth-order modulators. The simulated data is obtained within a Matlab/Simulink® environment and is valid for a particular topology. The data graphics help the designer to exploit the performance of the topology as they provide insight of how the SNR and MSA are affected when more aggressive noise transfer functions are synthesized. A case study that compares second- and third-order modulators, designed for a given application, is analyzed to find the more efficient architecture in terms of circuit complexity and robustness against non-idealities.

Direct Feedback Topology for Reducing Residual Voltage in Functional Electrical Stimulation

Implantable functional electric stimulation (FES) systems are currently being investigated as treatment for some types of neural dysfunctions. For this purpose, several neural stimulator systems on a chip (SOCs) have been proposed for: deep brain stimulation (DBS), cochlear prosthesis, visual prosthesis (VP), and artificial limbs control. Two major and related issues in FES are the charge balancing and Faradaic currents. When stimulation currents have DC components, or if residual voltage persists accross electrodes, the accumulated electronic charge is converted into ionic species, thus feeding irreversible Faradaic reactions that damage electrodes and necrose tissues. This article introduces circuit solutions for balancing functional electrical stimulation whilst reducing residual voltages at electrodes. The circuit consists of four blocks: an ultra-low-power charge-redistribution digital-to-analog converter (CR-DAC), a feedback mechanism, a high-voltage H-bridge and a digital controller. To prove the effectiveness of the proposed topology a circuit is being designed in CMOS UMC 130nm technology, and simulation results suggest that proposed technique allows to keep electrode voltage under safe limits, smaller than 28mV.

A charge-redistribution based controller for keeping charge balance in neural stimulation

In this article, we present a circuit solution for sensing and controlling functional electrical stimulation (FES) currents. The objective is to keep both charge balance and residual electrode voltage under a safe limit throughout stimulation. In the proposed circuit, the stimulation current is set through an ultra-low-power charge-redistribution digital-to-analog converter (CR-DAC). Each stimulation pulse is copied by high-ratio current mirror into switched capacitors which integrate the residual direct current (DC) resulting from FES imbalances. As residual electrode voltage may buildup even for perfectly balanced current pulses, alternated cathodic-first and anodic-first stimulation is adopted to complement the charge-balancing mechanism. Simulation results suggest that the circuit is able to keep both residual charge and electrode voltage under safe limits, smaller than 0.05% and 64 mV respectively.

System-Level Design of a Reconfigurable CT SD Modulator for Multi-Standard Wireless Applications

This paper reports the system-level design of a reconfigurable continuous-time sigma-delta modulator that is capable to perform the analog-to-digital conversion for GSM, LTE5 and WLAN wireless standards. The modulator architecture consists of a third-order loop filter using feed-forward summation topology and a 4-bit internal quantizer. The modulator coefficients were directly synthesized in the continuous-time domain which provides a more efficient modulator in terms of noise shaping, efficiently placing the zeros and poles of the noise transfer function. The reconfiguration strategy is performed at the circuit-level by using digital signals that selects the appropriate transconductances, capacitors and the sampling frequency for each standard. SIMULINK building blocks that model the non-idealities associated with the modulator were employed in the system-level simulations. The results show that the modulator achieves a signal-to-noise plus distortion ratio of 96/83/81 dB within a 0.2/5/10 MHz signal bandwidth.

High-order low-distortion switched-current cascade 2–2–2 ΣΔ modulator

This paper presents the design and simulation results of a switched-current (SI) MASH 2-2-2 Sigma-Delta Modulator (ΣΔM). The modulator makes use of a low-distortion swing suppression topology which is highly suitable for wideband and high-order modulators. Simulation results reveal that peak signal to noise plus distortion ratio (SNDR) is 83.5 dB at 5 MHz sampling rate with 10 kHz bandwidth. The modulator was designed in a 0.6 μm CMOS technology and the power dissipation is about 45 mW.

14-bit DR, 20 kHz BW, 2-2 MASH SI-Σ㪔 modulator using low-distortion feedforward topology

This paper presents the design and simulation results of a switched-current (SI) 2-2 MASH Sigma-Delta Modulator (ΣΔM). The modulator is composed by a low-distortion swing suppression topology which is highly suitable for wideband applications. It was realized using fully-differential circuitry with common-mode feedback. The circuit performs 14-bit dynamic range (DR) up to 5 MHz clock frequency and 20 kHz bandwidth. The modulator was designed in 0.6 μm CMOS technology and was sent to the foundry to prototype.