André Luiz Aita

Design of an integrated low power high CMRR instrumentation amplifier for biomedical applications

This paper presents the design of a low-power high-CMRR CMOS instrumentation amplifier (IA) aimed for biomedical applications. The amplifier fundamentals were initially presented followed by its main building blocks. Simulation and experimental results were presented and discussed. The IA circuit was designed in AMIS 1.5 µm technology and manufactured through the MOSIS Service. The measured gain,CMRR and power consumption were 65dB, 120dB and 100uW respectively.

A 0.45V CMOS relaxation oscillator with ±2.5% frequency stability from −55°C to 125°C

Low-power and low-voltage oscillators are critical for many autonomous systems. Ultra low-power and low-voltage operation can enable these systems to remain functional under extreme supply conditions while consuming very little energy. Stable operation under these conditions and over a wide temperature range can be very challenging. This paper1 presents the design of a relaxation oscillator that operates under 0.5V and consumes less than a 100nW and is thus suitable for many autonomous applications. Despite of the low supply voltage, simulation results shows a relaxation oscillator with a frequency stability better than ±2.5% from -55°C to 125°C.

PTAT CMOS current sources mismatch over temperature

Proportional to Absolute Temperature (PTAT) CMOS current sources are widely used in temperature sensors, bandgap references, and other temperature-compensating circuits. Most of these applications strongly rely on the accuracy of a current ratio m established with a set of 1+m PTAT current sources. However, a PTAT CMOS current source has a temperature-dependent bias point, which in turn, has a well-known effect on the mismatch of CMOS current sources. This paper analyzes the mismatching properties of PTAT current sources due to variation of the current-sources bias point (gm/IDS) with temperature, from -55°C to 125°C. After the analysis, the paper shows measurements of a precision temperature sensor without mismatch compensation to corroborate the analysis developed.

A 1-V PTAT current reference circuit with 0.05%/V current sensitivity to VDD

This paper presents a CMOS PTAT current reference circuit which is robust against process and supply voltage variations over a wide voltage and temperature range, i.e. from 0.9 V to 2.5 V and from -40° C to 125° C, respectively. Two implementations of the same circuit were designed for comparison: the first one uses core transistors (1.1 V), while the second one employs IO transistors (2.5 V). The circuit uses a PMOS version of a conventional PTAT current generator with a PMOS self-cascode MOSFET and a PMOS feedback amplifier to enhance the circuit performance. Simulation results have shown a PTAT current sensitivity to the supply voltage of 2.9%/V @ 27° C (from 0.9 V to 1.5 V) and of 0.05%/V @ 27° C (from 1 V to 2.5 V) for core and IO transistors implementations, respectively, and a nearly constant current spread over temperature, with a maximum variation of 10% (3σ) for both ones.

System-level Design of Single-bit Sigma-Delta Modulators Based on MSA and SNR Data Graphics

This paper presents a more comprehensive approach for the design of single-bit single-loop sigma-delta modulators, either in continuous or discrete-time domain. The approach is based on SNR and MSA data graphics generated for second-, third- and fourth-order modulators. The simulated data is obtained within a Matlab/Simulink® environment and is valid for a particular topology. The data graphics help the designer to exploit the performance of the topology as they provide insight of how the SNR and MSA are affected when more aggressive noise transfer functions are synthesized. A case study that compares second- and third-order modulators, designed for a given application, is analyzed to find the more efficient architecture in terms of circuit complexity and robustness against non-idealities.

VHDL control system for linear ultrasonic motors

Ultrasonic Motors are devices with micro or even nano-positioning capabilities. This feature derives from voltage-strain characteristic of piezoelectric ceramics. Furthermore, to accomplish fine positioning, a high resolution control system is required. This paper presents simulated results from a VHDL description of a micro-positioning control system for linear traveling wave ultrasonic motors (TWUSM). The controller is dedicated to TWUSM control, and uses motor dynamic characteristics for estimating the exact slider end positioning point, from real time acquired data.

A low-price platform to test digital integrated circuits using FPGA

In this paper, we describe a low-price method to test integrated circuits using the same test vectors in the gate, transistor and device levels of abstraction. A test program often generates hundreds of thousands of different test vectors applied at a frequency of several megahertz over several hundred milliseconds. Production testers are large machines that take up their own room and are very expensive (typically well over

Virtual Collaborative Environment for Support of Teamwork-based Education of Analog IC Design

1 million). Either the customer, or the ASIC manufacturer, or booth, develop the test program. Two things are necessary before virtual integration and test can be accomplished. The first is the ability to simulate the hardware at speeds sufficient to make software execution a reality. In most cases, this means that the hardware simulation performance must be increased by a factor of at least 1000 over current execution speeds. The second is the need to bring the debug and development environments of the hardware and software closer together. In order to describe here the proposed method, the test of a circuit is presented. The DUT (device under test) used as example is a digital integrated circuit that implements a novel architecture for multiplication. The multiplier integrated circuit was designed using Xilinx and Mentor Graphics tools and fabricated in AMI_C5F technology. Results have shown that the idea can be easily extended to 16 or 32 bits and the frequency operation is directly dependent of the FPGA board used. Test vectors up to 50 MHz were being employed with a depth equal to 100