Cesar Ramos Rodrigues

An 8-bit 0.35-V 5.04-fJ/Conversion-Step SAR ADC With Background Self-Calibration of Comparator Offset

This paper reports a successive approximation register (SAR) analog-to-digital converter (ADC) based on the charge-sharing principle, which is known to be very energy efficient, but susceptible to the comparator offset. The ADC uses a new background calibration technique to cancel out the comparator mismatch and improve ADC linearity. Operation under low voltages is obtained through the use of voltage-boosted switches in the track-and-hold and the digitalto-analog converter. The techniques are demonstrated on a low-voltage low-power SAR ADC that operates from a minimum supply voltage of 350 up to 600 mV, suitable for circuits supplied by power harvesters. The prototype fabricated in a 130-nm CMOS process employs only regular-VTH transistors. It is able to convert at 3 MSps when supplied by 600 mV and at 200 kSps when supplied by 350 mV. At 350 mV, the measured effective-number-of-bits is 6.4, leading to a figure-of-merit of 5.04 fJ/conversion-step.

Automated drowsiness detection through wavelet packet analysis of a single EEG channel

Ratio indices computed from a single EEG channel used as drowsiness indicators.Delta and gamma brain rhythms successfully used for drowsiness detection.Wavelet packet transform as the main tool to localize specific brain frequency ranges.Transition from alert to drowsy state is taken as main event of interest.Wilcoxon signed rank test analysis pointed out the contribution of proposed indices. Advances in materials engineering, electronic circuits, sensors, signal processing and classification techniques have allowed computational systems to interpret biological quantities, recognizing physiological conditions. The next scientific challenge is to turn those technologies portable, wearable or even implantable, above all, being energy efficient. A prospective application for the next generation of portable electroencephalogram (EEG) signal processing systems is hazard prevention in attention-demanding activities. EEG keeps closest connection to the preoptic area where sleep is originated. In this paper, a methodology for assessing alertness level based on a single EEG channel (Pz-Oz) is proposed, allowing the reduction of the required hardware and the computational time of the algorithms, besides being more portable than multi-channel based ones. Two new spectral power-based indices (i) γ/? and (ii) ( γ + β )/( ? + α ) are computed from EEG rhythms through the normalized Haar discrete wavelet packet transform (WPT). The Haar WPT allows precisely resolving the brain rhythms into packets whilst demanding a relatively low computational cost. The effectiveness of the proposed indices in drowsiness detection is evaluated by comparison with five indices originally proposed for multi-channel processing. Statistical Wilcoxon signed rank test is applied to evaluate the performance of the entire set of indices, evidencing the significant changes in the alert-drowsy transitions of 20 subjects of a public database. The proposed indices (ii) and (i) presented the most and second more significant p-Values (p < 0.001 and p?=?0.001), respectively.

Design of an integrated low power high CMRR instrumentation amplifier for biomedical applications

This paper presents the design of a low-power high-CMRR CMOS instrumentation amplifier (IA) aimed for biomedical applications. The amplifier fundamentals were initially presented followed by its main building blocks. Simulation and experimental results were presented and discussed. The IA circuit was designed in AMIS 1.5 µm technology and manufactured through the MOSIS Service. The measured gain,CMRR and power consumption were 65dB, 120dB and 100uW respectively.

A switched current sigma delta modulator using a low distortion feedfoward topology

Implementation of feedforward paths for low-distortion topologies on switched capacitor sigma-delta (SC-SD) modulators was successfully reported elsewhere [13]. In this paper we propose the use of a similar low distortion topology on an implementation of a switched current sigma-delta (SI-SD) modulator. The objective is a reduction of harmonic distortion observed in implementations with simple integrator cells. In this approach, one of the main SI cell drawbacks, the harmonic distortion due to conductance variation, can be reduced by alleviating the signal in the integrators path. In this approach, the integrators ideally process only noise. Relaxing requirements of integrators allows simpler and faster switched-current integrator circuits. The feedforward SI-SD modulator was designed in XFAB CMOS 0.6µm technology. Simulated results points to a reduction of harmonic distortion from 2% in a classical 2nd order feedback topology to 0.2% in the feed forward design. It also provides a reduction of 30% in the silicon area, and higher sampling frequency.

Instrumentation Amplifier using Robust Rail-to-Rail Operational Amplifiers with gm Control

An instrumentation amplifier based on constant gm, rail-to-rail transconductance amplifiers is presented. The circuit was designed to 0.5 mum AMIS CS CMOS technology. Simulation results show that a -3 dB bandwidth about 190 kHz could be obtained. Operating with a 3 V supply and its dc gain set to 66 dB, the amplifier has a power consumption of 110 muW, and a CMRR higher than 140 dB.

An energy-efficient 1MSps 7µW 11.9fJ/conversion step 7pJ/sample 10-bit SAR ADC in 90nm

Current trends constantly increase the need for ultra-low power solutions for the embedded and portable hardware. One circuit component required in wide range of devices is the analog-to-digital converter (ADC). In this paper we propose an extremely energy-efficient successive approximation register (SAR) ADC, in which we have overcome the limitations of conventional approaches through topological improvements. Further, advances include a novel bootstrapped track and hold (T/H) circuitry. Statistical simulations indicate an ADC with a figure of merit (FOM) of 11.9 fJ per conversion step, and an effective number of bits (ENOB) of 9.2, operating close to Nyquist frequency, sampling at 1 Msps. To put it into perspective, consuming only 7 pJ/sample, this ADC is able to work at its maximum speed for more than 40 years with the total energy of a single alkaline AA battery.

A 4-bit 1.5GSps 4.2mW comparator-based binary search ADC in 90nm

Traditional ADC architectures often fail to provide the required balance between low-power and high sampling rate, leaving room for further topology exploration. We propose a modified binary search ADC topology, which relies on a pipeline for the comparator stages and tracks the input in a time-interleaved fashion. Extensive statistical simulations for the 4-bit proposed ADC show that, sampling at 1.5GSps, the ADC consumes 4.2mW, providing 3.67 effective bits and a figure of merit of 219fJ/conversion step, without requiring calibration.

A track and hold for single-ended or differential input with adjustable output common mode

A novel differential output track and hold (TH) circuit with configurable common-mode output voltage is presented. Its structure avoids the coupling circuits required when dealing with different common-mode levels in differential signals. Another novelty of the proposed design is its ability to track single-ended signals, and convert the output to a steady differential voltage, with a programmable common-mode level. The solution employs switched capacitors arrangement that is compatible with standard CMOS technology. Circuit simulations in a 90nm technology for both single-ended and differential input confirm the ability of convert and stabilize the output common mode (CM) levels. The main drawback is a small loss of output linearity (4.81dB and 2.72dB for single-ended and differential input, respectively).

A 5-bit 1.5GSps calibration-less binary search ADC using threshold reconfigurable comparators

Modern RF communication technologies often shift the baseband processing to the digital domain, thus requiring an analog-to-digital converter (ADC) as interfacing element. For most applications, those ADCs must provide very-high conversion rate at low cost (effective in terms of area and power). We propose an improved binary-search ADC topology, which relies on a pipeline of threshold-reconfigurable comparators and a time-interleaved track-and-hold arrangement. We also propose a topology of threshold-reconfigurable comparator and a corresponding effective design methodology based on optimization through genetic algorithms. In this paper, we design a proof-of-concept 5-bit ADC which does not require calibration as most similar designs. Monte Carlo simulations for the proposed design show that, sampling at 1.5 GSps, the ADC consumes 5 mW providing 4.6 effective bits and a figure of merit of 138 fJ/conversion step (mean values).

A novel energy efficient digital controller for charge sharing successive approximation ADC

Successive approximation analog-to-digital converters are very attractive to power-constrained applications due to the topology inherent energy efficiency. This converter architecture most often relies on digital controller circuit to guide the conversion algorithm, and this controller is reported to have an important impact on the overall power consumption, sometimes demanding roughly half the total energy of a given ADC. Therefore, the design of an efficient controller must be of main concern in an ultra-low power ADC. In this paper we present a novel full-custom controller, based on true single phase clock latch, and provide simulation results. The proposed implementation achieves an extreme power reduction using only 13.4% of the energy of a standard cells implementation. We also propose a figure of merit (FOM) to controllers, and use it to compare our topology to a range of state-of-the art ADCs. According to this FOM, the proposed controller exhibits the smallest amount of energy per processed bit currently reported for SAR ADCs.