João Baptista dos Santos Martins

Montgomery modular multiplication on reconfigurable hardware: Fully systolic array vs parallel implementation

This paper describes a comparison of two FPGA Montgomery modular multiplication architectures: a fully systolic array and a parallel implementation. The modular multiplication is employed in modular exponentiation processes, which is the most important operation of some public-key cryptographic algorithms and the most popular of them is the RSA encryption scheme. The proposed fully systolic array architecture presents a high-radix implementation with carry propagation between the Processing Elements. The parallel implementation is composed by multipliers blocks in parallel with the Processing Elements and it provides a pipelined operation mode. We compared the time x area efficiency for both architectures as well as a RSA application. The fully systolic array implementation can run the 1024 bit RSA decryption process in just 3.23 ms and the parallel architecture executes the same operation in 6 ms, which means a competitive state-of-art performance for both architectures.

Montgomery modular multiplication on reconfigurable hardware: systolic versus multiplexed implementation

This paper describes a comparison of two Montgomery modular multiplication architectures: a systolic and a multiplexed. Both implementations target FPGA devices. The modular multiplication is employed in modular exponentiation processes, which are the most important operations of some public-key cryptographic algorithms, including the most popular of them, the RSA. The proposed systolic architecture presents a high-radix implementation with a one-dimensional array of Processing Elements. The multiplexed implementation is a new alternative and is composed of multiplier blocks in parallel with the new simplified Processing Elements, and it provides a pipelined operation mode. We compare the time × area efficiency for both architectures as well as an RSA application. The systolic implementation can run the 1024 bits RSA decryption process in just 3.23 ms, and the multiplexed architecture executes the same operation in 4.36ms, but the second approach saves up to 28% of logical resources. These results are competitive with the state-of-the-art performance.

A Gigabit UDP/IP network stack in FPGA

This paper presents a proposal of a Gigabit UDP/IP network stack in FPGA, which is the stack of the widely used in VoIP and Video-conference applications. This network node implements the Network, Transport and Link Layer of a traditional stack. This architecture is integrated and developed using Xilinx ISE tool and synthesized to a Spartan-3E FPGA. We show architecture details, timing and area results of a practical prototyping. Also, we compare our prototype and results with other works in terms of area (Xilinx slices), speed (MHz), maximum Ethernet frame length (bytes) and maximum Ethernet speed (Mbps). Comparing to these works our architecture obtained a intermediate solution in area and is the best implementation in terms of speed (MHz).

Design of pipelined butterflies from Radix-2 FFT with Decimation in Time algorithm using efficient adder compressors

This paper addresses the use of efficient adder compressors in dedicated structures of Radix-2 Decimation in Time (DIT) pipelined butterflies aiming the implementation of low power Fast Fourier Transform (FFT) architecture. In the FFT computation, the butterflies plays a central role, since they allow calculation of complex terms. In this calculation, involving multiplications of input data with appropriate coefficients, the optimization of the butterfly can contribute for the reduction of power consumption of FFT architectures. In this paper different and dedicated structures for the 16 bit-width pipelined radix-2 DIT butterfly running at 100MHz are implemented, where the main goal is to minimize both the number of real multipliers and the critical path of the structures. This is done by changing the structure of the complex multipliers and applying them into the butterflies. For logic synthesis of the implemented butterflies it was used Cadence Encounter RTL Compiler tool with XFAB MOSLP 0.18µm library. Area and power consumption results are presented for the synthesized butterflies. Regarding power consumption, switching activity analysis is performed using 10,000 inputs vectors at inputs of the butterflies. The main results show that when combining the use of pipeline approach and the use of efficient adder compressors, the power consumption of the butterflies is significantly reduced.

Design of an integrated low power high CMRR instrumentation amplifier for biomedical applications

This paper presents the design of a low-power high-CMRR CMOS instrumentation amplifier (IA) aimed for biomedical applications. The amplifier fundamentals were initially presented followed by its main building blocks. Simulation and experimental results were presented and discussed. The IA circuit was designed in AMIS 1.5 µm technology and manufactured through the MOSIS Service. The measured gain,CMRR and power consumption were 65dB, 120dB and 100uW respectively.

A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures

This paper presents performance comparisons between two multipliers architectures. The first architecture consists of a pure array multiplier that was modified to handle the sign bits in 2’s complement and uses a radix-4 encoding to reduce the partial product lines. The second architecture implemented was the widely used Modified Booth multiplier. We describe a design methodology to physically implement these architectures in a pipelined and non-pipelined form, obtaining area, power consumption and delay results. Up to now only results at the logic level were presented in previous work. The performance of pipelined array architecture is compared with the pipelined Modified Booth. We compare the physical implementations in terms of area, power and delay. The results show that the new pipelined array multiplier can be significantly more efficient, with close to 16% power savings and 55% power savings when considering non-pipelined architectures. 2 Leonardo L. de Oliveira, Cristiano Santos, Daniel Ferrao, Eduardo Costa, Jose Monteiro, Joao Baptista Martins, Sergio Bampi, Ricardo Reis

Interconnection Length Estimation at Logic-Level

Accurate and fast interconnection length estimation of CMOS circuits during the design phase is essential to evaluate placement, routing and power estimation. The goal of this work is to estimate the average interconnection length of the nets for a given circuit at the logic level. We propose a look-up-table method, taking into account three parameters available at the logic level: number of cells, number of nets and fanout of each cell. To validate the method we use an automatic layout generator, TROPIC3, which generates the circuit layout from a SPICE netlist, reporting the net lengths after synthesis. The proposed method is compared with the values obtained after layout synthesis. The difference between estimated length and real length are lower then 10%.

System-level Design of Single-bit Sigma-Delta Modulators Based on MSA and SNR Data Graphics

This paper presents a more comprehensive approach for the design of single-bit single-loop sigma-delta modulators, either in continuous or discrete-time domain. The approach is based on SNR and MSA data graphics generated for second-, third- and fourth-order modulators. The simulated data is obtained within a Matlab/Simulink® environment and is valid for a particular topology. The data graphics help the designer to exploit the performance of the topology as they provide insight of how the SNR and MSA are affected when more aggressive noise transfer functions are synthesized. A case study that compares second- and third-order modulators, designed for a given application, is analyzed to find the more efficient architecture in terms of circuit complexity and robustness against non-idealities.

System-Level Design of a Reconfigurable CT SD Modulator for Multi-Standard Wireless Applications

This paper reports the system-level design of a reconfigurable continuous-time sigma-delta modulator that is capable to perform the analog-to-digital conversion for GSM, LTE5 and WLAN wireless standards. The modulator architecture consists of a third-order loop filter using feed-forward summation topology and a 4-bit internal quantizer. The modulator coefficients were directly synthesized in the continuous-time domain which provides a more efficient modulator in terms of noise shaping, efficiently placing the zeros and poles of the noise transfer function. The reconfiguration strategy is performed at the circuit-level by using digital signals that selects the appropriate transconductances, capacitors and the sampling frequency for each standard. SIMULINK building blocks that model the non-idealities associated with the modulator were employed in the system-level simulations. The results show that the modulator achieves a signal-to-noise plus distortion ratio of 96/83/81 dB within a 0.2/5/10 MHz signal bandwidth.

A full duplex implementation of Internet Protocol version 4 in an FPGA device

This paper describes an implementation in hardware of Internet Protocol version 4. Routing and addressing features were integrated with Network Interfaces and synthesized to a Stratix II FPGA device. Our work showed two implementations of a full duplex Internet Protocol version 4. The first implementation consists in a Reference design and the second uses the same design but with more buffer space. We present the advantages and disadvantages of each implementation and also compare in terms of throughput, frame loss rate and power dissipation. The implementation with more buffer space presents a better performance in frame loss rate but it dissipates more power than the Reference design. Both implementations presented similar results for throughput tests.