Chai Ean Gill

A convergence robust method to model snapback for ESD simulation

A new behavior modeling method is presented to model ESD protection devices with voltage snapback. It resolves the convergence problem induced by snapback characteristic. The model can pass HBM, MM and TLP transient simulations in SPICE. The reason for convergence robustness is also discussed.

Unique ESD failure mechanism of high voltage LDMOS transistors for very fast transients

We have identified and explained a unique ESD breakdown mechanism of high voltage 80V LDMOS structures for very fast CDM transients. The device was protected against observed damage by placing a zener across the gate and source which prevents the observed voltage build up at the gate of the LDMOS.

Techniques to prevent substrate injection induced failure during ESD events in automotive applications

This paper presents several techniques to improve ESD robustness for high voltage IO designs in automotive applications. SCR-based ESD clamps designed on isolated wells can generate high level of substrate injection during ESD events, causing false triggering and irreversible failures of internal components. To mitigate substrate injection effects, we have defined design strategies leading to a set of designs rules for proper integration with ESD clamps.

CDM protection of high voltage LDMOS for automotive applications

In recent years, CDM compliance has been widely accepted as a critical part of product qualification to ensure product robustness. Hence technologies developed to support automotive market has increasingly required full AEC-Q100 ESD compliance to include a minimum of 500 V CDM robustness in addition to HBM and MM specifications. The high voltage devices developed to support 45 V to 80 V pins are typical requirements for automotive designs to support inductive loading from solenoid current which can generate dual polarity peak transients. The ESD protections designed for these pins need to be very compact high current device capable of clamping +65 V in forward mode coupled with -5 V in reverse mode. These ESD protections must also respond to transients of rise time (tr) ranging from 10 ns to 100 ps to protect against HBM to CDM stress. This paper will present CDM design strategy to protect high voltage laterally diffused MOS (LDMOS) devices, requiring both primary and secondary ESD protection circuitry for 750 V CDM compliance.