Amaury Gendron

TCAD Methodology for ESD Robustness Prediction of Smart Power ESD Devices

This paper presents a new method to predict the electrostatic-discharge (ESD) protection robustness of a device with technology-in-computer-aided-design (TCAD) simulations. Tested on different devices and two Smart Power technologies, the results are validated through electrical measurement and failure analysis. Failure current is always predicted with a good accuracy compared to technology spreading. In addition, the methodology provides a significant simulation time speedup compared to classical methods based on a temperature criterion

High robustness PNP-based structure for the ESD protection of high voltage I/Os in an advanced smart power technology

A new device dedicated to the ESD protection of high voltage I/Os is presented. In addition to the use of specific design guidelines, the concept consists in coupling an open-base lateral PNP with a vertical avalanche diode within the same structure to obtain a non-snapback behavior together with very good Ron capabilities (~1Omega). The protection of high voltage I/Os with a narrow ESD design window ranging from 80 V to 100 V can be implemented in a reduced surface of 151*140 mum2, which represents a state-of-the-art breakthrough.

Transient voltage overshoots of high voltage ESD protections based on bipolar transistors in smart power technology

Transient voltage overshoots of a high voltage (20 V) ESD clamp based on bipolar transistors in a smart power technology are studied using different TLP pulse conditions (rise time, voltage amplitude). The physical mechanisms involved during the ESD clamp turn-on are thoroughly analyzed by the mean of TCAD simulations, allowing the definition of a set of design guidelines for the overshoot reduction.

Unique ESD failure mechanism of high voltage LDMOS transistors for very fast transients

We have identified and explained a unique ESD breakdown mechanism of high voltage 80V LDMOS structures for very fast CDM transients. The device was protected against observed damage by placing a zener across the gate and source which prevents the observed voltage build up at the gate of the LDMOS.

Deep Trench NPN Transistor for Low-RON ESD Protection of High-Voltage I/Os in Advanced Smart Power Technology

An innovative self-biased NPN transistor dedicated to the ESD protection of high voltage I/Os is presented. To fulfil a high clamping voltage / low on-state resistance specification, the authors have taken benefit of specific technology features, as deep insulation trenches, low-doped epitaxy and high-doped buried layer. First, the guidelines allowing the increase of the clamping voltage and the lowering of the on-state resistance are defined, based on an accurate description of the physical mechanisms involved during an ESD stress. Then, the proposed NPN transistor is described, and the results of measurements and TCAD simulations are presented. Excellent capabilities as 40 Volt clamping voltage, zero on-state resistance and It2 higher than 5 Ampere have been achieved

Techniques to prevent substrate injection induced failure during ESD events in automotive applications

This paper presents several techniques to improve ESD robustness for high voltage IO designs in automotive applications. SCR-based ESD clamps designed on isolated wells can generate high level of substrate injection during ESD events, causing false triggering and irreversible failures of internal components. To mitigate substrate injection effects, we have defined design strategies leading to a set of designs rules for proper integration with ESD clamps.