Chandrajit Debnath

20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process

This paper describes a novel low power 10-bit 125 Msps pipelined ADC implemented in 65 nm standard digital CMOS process. Proposed ADC implements 2.5 b/stage with amplifier shared between consecutive stages, achieves best in class FOM of 0.27 pJ/step with conversion power of 0.16 mW/Msps. The ADC amplifier employs novel techniques of adaptive biasing and cross coupled compensation to achieve improved settling behavior with significant power efficiency. This ADC occupies 0.13mm area and achieves maximum 0.3 LSB DNL and 0.6 LSB INL along with 9.26 ENOB at 125 Msps dissipating 20 mW power from 1.2v supply.

A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process

This paper describes an 11 b ADC realized using a 2.5 b pipelined stage followed by 9 b time interleaved SAR. Presented ADC designed in 65 nm CMOS process occupies 0.3 mm2 area, achieves 59.1 dB SINAD at 100 Ms/s sampling frequency while dissipating 15 mW power from 1.2 V supply and resulting FOM is 0.20 pJ/step.

A 0.065-mm 2 19.8-mW Single-Channel Calibration-Free 12-b 600-MS/s ADC in 28-nm UTBB FD-SOI Using FBB

A 0.065-mm2 single-channel calibration-free 12-b analog-to-digital converter (ADC) sampling at 600 MS/s in 28-nm ultrathin body bias fully depleted silicon on insulator (FD-SOI) is presented. The selected hybrid architecture, incorporating pipelined and asynchronous successive approximation register ADC, demonstrates advantages and suitability of different design techniques utilizing forward body bias (FBB) capability of FD-SOI. Using an FBB voltage range of 0–1.8 V has enabled an signal-to-noise plus distortion ratio (SNDR) improvement of more than 9 dB. An integrated body bias generator ensures the required voltages for FBB. This paper demonstrates 61.5-dB and 60.7-dB SNDR at low and Nyquist input frequency, respectively, at 600-MS/s sampling frequency. The Walden FoM of 37.2 fJ/conv-step and Schreier FoM of 162.5 dB at 600 MS/s are achieved in Nyquist conditions. Speed robustness of the architecture has been demonstrated by achieving 57-dB SNDR at 800MS/s, >50-dB SNDR up to 950 MS/s, and 58.5-dB SNDR till 500-MHz input frequency at 600 MS/s.

A 0.065mm 2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB

Most of the high speed low power ADCs are interleaved using calibration which have some drawback like calibration time, the complexity associated with calibration algorithm and its circuit implementation. Therefore a single channel calibration-free 12-bit ADC sampling at 600MS/s in 28nm UTBB FDSOI is presented. Selected ADC architecture of mixing Pipelined stage and Asynchronous SAR demonstrates advantages and suitability of different design techniques utilizing forward body bias (FBB) capability available for FDSOI CMOS. Measured silicon results show >9dB performance improvement with FBB voltage range of 0-1.8V. Integrated body bias generator (BBGEN) ensures required voltages for FBB. This work measures the 60.7dB SINAD at Nyquist frequency achieving Walden FOM of 37.2fJ/conv-step and Schreier FOM of 162.5dB at 600MS/s. It is also achieving 57dB SINAD at 800Ms/s, >50dB SINAD up to 950MS/s and 58.5dB SINAD till 500Mhz input frequency.