Ankur Bal

Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times

The high cost of mixed-signal circuit testing has sparked a lot of interest for developing alternative low-cost techniques. Although it is rather straightforward to evaluate an alternative test technique in terms of test cost reduction, proving the equivalence between an alternative and the standard test technique in terms of test metrics, before actually deploying the alternative test technique in production, is very challenging. The underlying reason is the prohibitive simulation effort that is required. Existing test metrics evaluation methodologies are efficient only for circuits that can be simulated fast at transistor-level. In this paper, we propose a test metrics evaluation methodology for circuits with long simulation times that is based on a combination of behavioral modeling and statistical blockade. The methodology is demonstrated on a built-in self-test strategy for ΣΔ analog-to-digital converters.

A 12b 1.7GS/s two-times interleaved DAC with <-62dBc IM3 across Nyquist using a single 1.2V supply

A two-times interleaved DAC using only a single supply voltage in a standard 65nm CMOS technology is presented. The interleaving architecture suppresses most of the non-idealities commonly found in high-speed DACs. Spurs generated by the interleaved architecture are suppressed by a novel calibration algorithm. The design achieves IM3 levels below -62dB across Nyquist with a clock frequency of 1.7GHz. The circuits active area is 0.4mm2 and the power consumption is 70mW from a nominal 1.2V supply.

Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques

Accurate and efficient evaluation of alternative test methods is required for analog/mixed-signal circuits. To address this need, this article presents a semiautomated practical simulation flow specifically targeting circuits with long simulation times.

A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio

This paper proposes a fully-digital BIST architecture for the dynamic test of ΣΔ ADCs. The proposed BIST relies on generating a ternary stream that encodes a high-linearity analog sinusoidal and injecting it directly at the input of the ΣΔ modulator. Compared to the well-known bitstream, the use of three logic levels in the ternary stream reduces the quantization noise and, thereby, results in a test with a higher dynamic range that covers the full scale of the ADC. The output response is analyzed on-chip using a simplified version of the sine-wave fitting algorithm to compute the SNDR. A standard SPI bus provides digital external access to the embedded test instruments. The proposed BIST wrapper has been integrated into a 40 nm CMOS 18-bit stereo audio ΣΔ ADC IP core provided by ST Microelectronics. It incurs an overall area overhead of 7.1% and the total test time is 28 ms per channel. Experimental results on fabricated chips demonstrate an excellent correlation between the BIST and the standard functional specification test.