Stéphane Le Tual

22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS

Todays applications such as broadband satellite receivers, cable TVs, and software-defined radios require highly efficient ADCs with high sampling rates and high resolutions. A time-interleaved ADC (TIADC) is a popular architecture used to achieve this goal. However, this structure suffers from mismatches between the sub-converters, which cause errors on the output signal, and more significantly, decrease the SFDR. These mismatches can be a severe limitation in applications such as satellite reception, where both narrowband and wideband signals are used. This paper introduces digital derivative-based estimation of timing mismatches. Gain, offset and skew mismatch calibrations are performed entirely in the digital domain through equalization.

22.3 A 20GHz-BW 6b 10GS/s 32mW time-interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI technology

To sustain ever-growing data traffic, modern wireline communication devices (over copper or fiber optic media) require a high-speed ADC in their receive path to do the digital equalization, or to recover the complex-modulated information. A 6b 10GS/s ADC able to acquire up to 20GHz input signal frequency and showing 5.3 ENOB in Nyquist condition is presented. It is based on a Master Track & Hold (T&H) followed by a time-interleaved synchronous SAR ADC, thus avoiding the need for any kind of skew or bandwidth calibration. Ultra Thin Body and BOX Fully Depleted SOI (UTBB FDSOI) 28nm CMOS technology is used for its fast switching and regenerating capability. The core ADC consumes 32mW from 1V power supply and occupies 0.009mm2 area. The FoM is 81fJ/conversion step.

A 3.2GHz-sample-rate 800mHz bandwidth highly reconfigurable analog FIR filter in 45nm CMOS

A 16-tap analog FIR filter with 3.2 GHz-clock achieves fully reconfigurable transfer functions over an 800 MHz range. Time domain convolution is realized by switching programmable transconductance values and exploiting a current integration technique to merge sampling, summing and anti-aliasing functions. The circuit draws 65 mW from a 1.1 V supply and occupies 0.15 mm2 in 45 nm CMOS.

A 0.065-mm 2 19.8-mW Single-Channel Calibration-Free 12-b 600-MS/s ADC in 28-nm UTBB FD-SOI Using FBB

A 0.065-mm2 single-channel calibration-free 12-b analog-to-digital converter (ADC) sampling at 600 MS/s in 28-nm ultrathin body bias fully depleted silicon on insulator (FD-SOI) is presented. The selected hybrid architecture, incorporating pipelined and asynchronous successive approximation register ADC, demonstrates advantages and suitability of different design techniques utilizing forward body bias (FBB) capability of FD-SOI. Using an FBB voltage range of 0–1.8 V has enabled an signal-to-noise plus distortion ratio (SNDR) improvement of more than 9 dB. An integrated body bias generator ensures the required voltages for FBB. This paper demonstrates 61.5-dB and 60.7-dB SNDR at low and Nyquist input frequency, respectively, at 600-MS/s sampling frequency. The Walden FoM of 37.2 fJ/conv-step and Schreier FoM of 162.5 dB at 600 MS/s are achieved in Nyquist conditions. Speed robustness of the architecture has been demonstrated by achieving 57-dB SNDR at 800MS/s, >50-dB SNDR up to 950 MS/s, and 58.5-dB SNDR till 500-MHz input frequency at 600 MS/s.

Session 27 overview: Hybrid and nyquist data converters

The traditional boundaries between classical data converter architectures are being dissolved. Hybrid combinations that optimally exploit CMOS technology strengths have emerged. This session demonstrates multiple innovative hybrid and Nyquist-rate data converters ranging from 1 kHz to 4 GHz bandwidths and SNR levels exceeding 100dB. Papers in this session demonstrate hierarchical time interleaving, capacitor and opamp-sharing, and time interleaving skew calibration. SAR ADCs utilizing charge-injection DACs, embedded mismatch and noise shaping, and sub-ADCs using Delta-Sigma or digital slope techniques are disclosed. A noise-cancellation technique combined with amplitude and timing error pre-distortion demonstrates improved IM3 performance in a current-steering DAC.

A 0.065mm 2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB

Most of the high speed low power ADCs are interleaved using calibration which have some drawback like calibration time, the complexity associated with calibration algorithm and its circuit implementation. Therefore a single channel calibration-free 12-bit ADC sampling at 600MS/s in 28nm UTBB FDSOI is presented. Selected ADC architecture of mixing Pipelined stage and Asynchronous SAR demonstrates advantages and suitability of different design techniques utilizing forward body bias (FBB) capability available for FDSOI CMOS. Measured silicon results show >9dB performance improvement with FBB voltage range of 0-1.8V. Integrated body bias generator (BBGEN) ensures required voltages for FBB. This work measures the 60.7dB SINAD at Nyquist frequency achieving Walden FOM of 37.2fJ/conv-step and Schreier FOM of 162.5dB at 600MS/s. It is also achieving 57dB SINAD at 800Ms/s, >50dB SINAD up to 950MS/s and 58.5dB SINAD till 500Mhz input frequency.

Session 11 overview: Data converter techniques: Data converters subcommittee

Power efficiency and high dynamic range are of crucial importance for contemporary data converters, which are essential in a wide range of demanding applications, such as medical, sensor, and advanced wireless mobile systems. Circuits and architectures tailored to low-voltage deep-submicron CMOS technologies, data-driven conversion and optimized calibration algorithms are presented in this session. These innovative data converter techniques and algorithms are advancing the state of the art in dynamic range and power efficiency.