Chang-Chih Liu

Performance and process characteristic of glass interposer with through-glass-via(TGV)

Primary approach of 3DIC packaging usually adopts organic substrates or silicon interposer as the intermedium between multi-integrated circuits (ICs) and printed circuit board. Current organic substrates face the limitations in poor dimensional stability, trace density and CTE mismatch to silicon. Silicon interposer is a good solution for high-pin-count ICs and high performance applications based on the mature Si technology of advance via formation and fine line Cu damascene multilevel interconnection process, but silicon interposer is limited by high cost. Glass is proposed as ideal interposer material due to high resistivity, low dielectric constant, low insertion loss and adjustable coefficient of thermal expansion (CTE) for the 3DIC assembly integration and most importantly low cost solution, [1-4]. The main focus of this paper is on (a) TGV electrical design, simulation and characterization, (b) wafer level integration in TGV formation, two RDL on the front-side, one RDL on the backside and polymer-based PBO for the passivation, (c) assembly process of silicon chip stack on the glass interposer with Kelvin resistance measurement. The glass interposer was assessed to have excellent electrical characteristics and is potentially to be applied for 3D product applications.

Growth of high-quality relaxed SiGe films with an intermediate Si layer for strained Si n-MOSFETs

An intermediate Si layer in Si1?xGex film, replacing the conventionally compositional graded buffer layer, was used to fabricate a relaxed SiGe substrate of high quality. The intermediate Si layer changes the relaxation mechanism of the SiGe thin film via the generation of {3?1?1} dislocation loops. The {3?1?1} dislocation loops are formed in the intermediate Si layer to prompt a state of relaxation in the SiGe overlayer, provide the defects for trapping of threading dislocations (TDs) and leave a SiGe top layer with low dislocation density. For the SiGe/Si/SiGe samples, the residual strain and TDs on the top SiGe layer are independent of the SiGe underlayer thickness. With a 700 nm thick Si0.8Ge0.2 overlayer, such a Si0.8Ge0.2/Si/Si0.8Ge0.2 heterostructure with a smooth surface has a TD density of 8.9 ? 105 cm?2 and 3% residual strain. Owing to the different main relaxation mechanisms in SiGe films, the surface root mean square roughness of this relaxed buffer with a low density of surface pits was measured to be about 3 nm, which is lower than that of the sample without any intermediate Si layer (13 nm). Relaxation of the SiGe overlayer depends on the thickness of the intermediate Si layer. Optimization on relaxation in the SiGe/Si/SiGe structure with an intermediate Si layer of 50 nm is done. Strained Si n-channel metal-oxide-semiconductor field effect transistors with various buffer layers were fabricated and examined. The effective electron mobility for the strained Si device with this novel substrate technology was found to be 80% higher than that of the Si control device. The SiGe thin films with the intermediate Si layer serve as good candidates for high-speed strained Si devices. The global strain in the Si channel with a SiGe/Si/SiGe buffer is still beneficial for short channel devices.

Thermal stability study of Si cap/ultrathin Ge/Si and strained Si/Si1-xGex/Si nMOSFETs with HfO2 gate dielectric

The thermal stabilities of MOSFETs with high-K gate dielectric on both Si/ultrathin Ge/Si (SGS) and strained Si on relaxed Si1?xGex (SS) substrates are studied. Though an initial drivability enhancement of 29% is shown for the SGS nMOSFET, annealing at 750 ?C has resulted in drastic degradation in its drivability, lowering its Id beyond that of the Si nMOSFETs by 52%. Despite lowering in the junction leakage current, Ge diffusion to the near surface region, indicated by Vth and surface roughness change, degrades the SGS device performance significantly. For the SS nMOSFET, drivability varies with Ge content, whereby a maximum of 86% improvement over that of the Si nMOSFET is observed for 30% Ge. In contrast to the SGS nMOSFET, the SS nMOSFET is able to retain its Id improvement, even after annealing at 950 ?C, as the in-plane tensile strain is preserved. Ge diffusion to the surface does not affect the device significantly, as the strained Si thickness is about 10 nm compared to a Si cap thickness of only 1.5 nm for the SGS substrate.

Design and implementation of ultra-thin SiP modules

In recent years, SiP (System-in-Package) or SOP (System on Package) technology has become an attractive solution for size reduction of mobile devices. Passive components such as inductors or capacitors can be integrated into the substrate. The dimension of embedded capacitors can be further reduced by using high dielectric constant material. Thus, size miniaturization and cost reduction can be easily achieved through the replacements of surface-mounted devices (SMDs) on the substrate.chip can be reduced. Wafer-level packaging technology, wafer thinning technology, buried ultra-thin chips technology, and embedded passive components technology are both integrated in this paper to achieve a miniaturized ultra-thin SiP module. The feasibility of the ultra-thin SiP technology was verified by using a GPS module. For high integration and flexible design, an eight-layered organic substrate process is used in this project.

The database of Embedded Passives for RF-SiP design

Embedded Passives (EPs) are considered an attractive option to design RF-SiP (System in Package) modules. EPs are benefit by the shortened interconnections between active or passive components, which can make better RF-SiP modules. In this paper, we propose the database of EPs for RF-SiP design. The database provides the corresponding parameters of EPs, such as electrical characteristics, structures and material properties. The well-arranged database can help users to make the optimal design of EPs. Then the database of EPs was implemented to design the matching circuit of a power amplifier. The feasibility of the database has been proved via this case.