Cheng-Ta Ko

Characterization and reliability assessment of solder microbumps and assembly for 3D IC integration

In this investigation, Cu/Sn lead-free solder microbumps with 10μm pads on 20μm pitch are designed and fabricated. The chip size is 5mm × 5mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability Assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but still achieve good plating uniformity. With the current process, the undercut is less than 1μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder micro bumped chip is bonded on a Si wafer (chip-to-wafer or C2W bonding). Furthermore, the micro-gap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips w/o underfill is measured and exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, SAT analysis, and cross-section with SEM analysis. The stacked ICs are evaluated by reliability tests, including thermal cycling test (−55⇆125°C, dwell and ramp times = 15 min). Finally, ultra find-pitch (5μm pads on 10μm pitch) lead-free solder microbumping is explored.

Chip Embedded Wafer Level Packaging Technology for Stacked RF-SiP Application

In this paper, chip to wafer stacking and embedding active components by wafer level technologies were described. The radio frequency (RF) module-like component was chosen as the test vehicle in this study. Analog wafer were treated to less than 50 mum thickness and then singulated. The thin chip were die bonded, by chip stacking method, on to the digital wafer and embedded by lamination of dielectric layers, Aginomoto build up film (ABF) in this case. Laser drilling process was adapted to open the via to the pads on the analog chips and digital wafers. The vias and traces were Cu plated to form the interconnection between the chips and the component IO pads. Results of this study show the benefits of the structure can provide more precise alignment and more reliable chip to wafer stacking without any voids or defects. Meanwhile, the presented wafer level process gives a much simple and cost effective package. Besides, high aspect ratio build up process by multi-layer ABF lamination and Cu interconnection were well developed. By the described process integration, vertical chip stacked and embedded RF module within 300mum thickness, excluding the solder ball, could be demonstrated. All the realization of this small size RF module will be revealed in more detail. Reliability tests such as the 288degC solder dipping and 260degC level 3 preconditioning test were carried out to further clarify the component property. Results of the reliability test and the corresponding failure analysis were described in this paper.

Wafer Bumping, Assembly, and Reliability of Fine-Pitch Lead-Free Micro Solder Joints for 3-D IC Integration

In this investigation, Cu-Sn lead-free solder microbumps on 10-μm pads with a 20-μm pitch are designed and fabricated. The chip size is 5 × 5 mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but to still achieve good plating uniformity. With the current process, the undercut is less than 1 μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder microbumped chip is bonded on an Si wafer using chip-to-wafer bonding technique. Furthermore, the microgap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips without the underfill is measured and it exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, scanning acoustic tomography analysis, and cross-section with scanning electron microscopy analysis. The stacked ICs are evaluated by reliability (thermal cycling) test (-55 to 125°C). Finally, ultrafine-pitch (5-μm pads on a 10-μm pitch) lead-free solder microbumping is explored.

Process, assembly and electromigration characteristics of glass interposer for 3D integration

Glass interposer is proposed as a superior alternative to organic and silicon-based interposers for 3DIC packaging in the near future. Because glass is an excellent dielectric material and could be fabricated with large size, it provides several attractive advantages such as excellent electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In this paper, we investigated the EM performance of Cu RDL line with glass substrate. Three different physical properties of glass materials were used for studying the EM performance of Cu RDL line. The used testing conditions are under 150~170 °C and 300~500mA. The glass type material with best performance was applied for glass interposer process integration and assembly investigation. Therefore, a wafer-level 300mm glass interposer scheme with topside RDLs, Cu TGVs, bottom side RDLs, Cu/Sn micro-bump and PBO passivation has been successfully developed and demonstrated in the study. The chip stack modules with glass interposer were assembled to evaluate their electrical characteristics. Pre-conditioning test was performed on the chip stacking module with the glass interposer to assess the reliability of the heterogeneous 3D integration scheme. All the results indicate that the glass interposer with polymer passivation can be successfully integrated with lower cost processes and assembly has been successfully developed and demonstrated in the study.

Wafer-to-wafer hybrid bonding technology for 3D IC

In this research, the wafer-level metal/adhesive hybrid bonding technology was developed to perform the 3D integration platform. Four kinds of polymer materials, BCB, SU-8, AL-Polymer, and PI, were evaluated as the bonding adhesive for hybrid collocation with metal. After realizing the bonding properties, the qualified ones were patterned on wafers, and sequentially bonded by metal bonding conditions. Two kinds of conditions were simulated, one is Cu-Sn eutectic bonding, and the other is Cu-Cu thermo-compression bonding. The compatibility between each polymer and metal was evaluated, and the application range of each material was established thereof. Furthermore, samples with hybrid scheme were fabricated to perform hybrid bonding and realize the compatibility in whole process. The micro-bump/Cu-pad size less than 20µm and thickness less than 5µm were designed for interconnection. The bonding quality and interface investigation on metal/adhesive were analyzed to make sure the interconnection and micro-gap filling between stacked wafers. The evaluation results of wafer-level hybrid bonding and material candidates will be disclosed in the paper.

Investigation of the process for glass interposer

Through glass via (TGV) interposer fabrication processes are critical techniques in 3D-IC integration, providing the short interconnection among different stacked chips and substrate. Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, flexibility with CTE and most importantly low cost solution. In this investigation, the glass interposer by using TSV industry equipment and tooling was evaluated and developed and there are many challenges for processing. For process, the major differences between Glass and Si interposer are method for via formation and isolation. The test vehicle for Glass interposer is successfully processed. Glass material is composed with SiOx, it is good isolation for electrical current. The polymer-based PBO is used for passivation. For structure of glass interposer, there is one RDL on the front-side and backside, respectively. The other structure is 2 RDL on the front-side and one RDL one the backside. The CD of through glass via is 30 μm, it is formed by Corning Co. Cu overburden and Ti barrier are removed by wet etching process. For top RDL (line-width = 20μm), Cu plating process with seed layer (Ti/Cu) wet-etching process is applied. The PBO material is used for passivation, the process temperature is blow 200°C. Top UBM (15μm in diameter; 4μm/5μm-thick Cu/Sn) is formed with a top passivation opening (15μm). The structure is analyzed and demonstrated by SEM analysis. All the results indicate that the glass interposer with polymer passivation can be preceded and the cost for process is cheaper than Si interposer.

Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies

Cu TSV combination with Cu/Sn micro-joint to form vertical interconnection is a good alternative for 3D integration. The insertion loss of two chip stack was evaluated by simulation to realize the signal transmission effects in high speed digital signaling via TSV and micro-joint interconnect. To satisfy the throughput and cost requirement for mass production in future, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding was demonstrated. Key techniques including TSV fabrication, micro-bumping, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. This paper presents a complete study of structure design, process condition, electrical and reliability assessment of the wafer-level 3D integration scheme. The 3D integration scheme was assessed to be with excellent electrical performance and reliability, and is potentially to be applied for 3D IC applications.

Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

In this paper, the warpage and thermal performances of fan-out wafer-level packaging (FOWLP) are investigated. Emphasis is placed on the characterization of the effects of FOWLP important parameters, such as chip size, chip thickness, package/chip area ratio, epoxy molding compound (EMC), chip EMC cap, reconstituted carrier material and thickness, and die-attach film, on the warpage after postmold cure and backgrinding of the EMC. The simulation results are compared to the experimental measurements. Also, the thermal performance (junction-to-ambient thermal resistance) of FOWLP with various chip thicknesses is characterized. Finally, some FOWLP important parameters affecting the warpage and thermal performances are recommended.

Cu/BCB hybrid bonding with TSV for 3D integration by using fly cutting technology

In this research, the wafer level Cu/BCB hybrid bonding with TSV for 3D integration by using fly cutting technology is proposed. As we know Cu bump surface is rough by electroplating, and BCB is spin-coated on Cu bump wafer induced high topography. Cu bump surface roughness and Cu/BCB co-planarization are improved by fly cutting to achieve good Cu to Cu and BCB to BCB bonding interface without any large bonding voids at 250°C for 30min, and the result of the bonding strength is evaluated by shear test. TSV fabrication, micro-bumping, hybrid bonding, wafer thinning and backside RDL formation are well developed and integrated to perform the 3D integration platform. Cu/BCB hybrid bonding with TSV for 3D integration is successfully developed and demonstrated in this paper.

Ultrathin glass wafer lamination and laser debonding to enable glass interposer fabrication

Interposer fabrication processes are applied in three-dimensional (3-D) integrated circuit (IC) integration to shorten the interconnection among different stacked chips and substrates. Because Si is a common material in semiconductor technology, Si interposers have been widely studied in many research activities. Compared with a Si wafer, glass substrates have the advantages of high resistivity, low dielectric constant, low insertion loss, adjustable coefficient of thermal expansion (CTE), and the possibility to use panel-size substrates as well as thin glass substrates (100 μm) to avoid the costly thinning process for realization of low-cost 2.5-D ICs. Thus, glass interposer fabrication is studied thoroughly in this paper. Thin glass wafers have reduced mechanical stiffness. Therefore, handling and shipping thin glass wafers (≤100 μm) throughout the semiconductor fabrication and packaging assembly processes are critical. Temporary wafer bonding technology is used in this study to bond a thin glass wafer to a carrier to improve the rigidity. Vacuum lamination technology is used in this study as a bonding process to enhance the costeffectiveness. After processing, the carrier is removed by laser debonding. The thin glass wafer with structures on both sides does not need to undergo a glass thinning process and saves a lot of cost compared to the traditional glass or Si interposer processes. Thin 300-mm glass wafers 100 μm thick are evaluated as: (a) blank thin glass wafers and (b) thin glass wafers with through-glass vias (TGVs) 30 μm in diameter. A UV laser with a wavelength of 308 nm, which has the benefit of less impact to the device, was adopted to laser debonding. This method also has several benefits such as high throughput, low temperature, zero-force debonding, and possible selective laser debonding. Adhesive and release layers are key enabling materials for thin glass handling. In addition, the use of a laminator for temporary bonding and laser debonding are included in this study. Based on the excellent fabrication, the thin glass interposer has great potential to be applied in 2.5-D integration applications.