Chang-Gyu Hwang

Highly manufacturable process technology for reliable 256 Mbit and 1 Gbit DRAMs

Ta/sub 2/O/sub 5/ dielectric on poly-Si cylinder capacitors, chemical-mechanical polishing (CMP) planarization, pure W bit-line, and Al reflow were integrated into a highly manufacturable DRAM process technology. This technology provided larger process margin, higher reliability, and better design flexibility. In addition, the critical steps of the new process has been reduced by 25% of those of the conventional process. The manufacturability of the technology has been proven by applying it to 16 Mbit density DRAMs with 256 Mbit design rule (0.28 /spl mu/m).<<ETX>>

Design and characterization of analog VLSI neural network modules

A systematic method for testing large arrays of analog, digital, or mixed-signal circuit components that constitute VLSI neural networks is described. This detailed testing procedure consists of a parametric test and a behavioral test. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Stochastic analysis of the parametric test results can be used to predict chip yield information. Several measurement results from two analog neural network processor designs that are fabricated in 2 mu m double-polysilicon CMOS technologies are presented to demonstrate the testing procedure. >

New Paradigms in the Silicon Industry

The advances in silicon technology that have been the backbone of tremendous previous growth, was foreseen in 1965 when Gordon Moore published his famous prediction about the constant growth rate of chip complexity. And, in fact, it has repeatedly been shown that the number of transistors integrated into silicon chips has indeed doubled every 18 months. Increases in packing density, according to Moores law, are driven by two factors: reductions in production costs and increases in chip performance. Another prominent example of the unstoppable pace of technology advancement, where new sources of momentum are able to maintain or accelerate a growth trend, was predicted by the author of this paper: the time required for the market to witness a doubling of the density of NAND flash memory has been maintained within the period of one year over each of the past seven years. The primary aim of this paper to present various possible paths to maintain the technology-scaling trend beyond the 20 nm node. As will be shown, these solutions include not only 3D (three-dimensional) technologies but also non-silicon technologies on a molecular scale. In addition, new applications, and new growth engines for the semiconductor industry will be provided from a fusing of separate technologies such as silicon-based IT (information technology) with new materials or even new concepts

Semiconductor memories for IT era

Information technology (IT) emerged from the 1970s based on main-frame computers. Since then, PCs and the Internet world have drastically expanded the IT industry along with rapid growth of network and communication technology. For almost all platforms, semiconductor memories have been a key enabling technology. In the PC era, DRAM density increase has been driven by rapid expansion of applications with advanced operating systems. In the future, servers will continue driving high-density DRAM requirements, and the maximum memory size of servers will be one of the key performance parameters. 512 Mb DRAM will be widely available in 2002 and 16 Gb DRAM is expected to appear within the next 10 years. Performance of semiconductor memories will be driven by graphics applications and network systems. 1 Gb/s/pin DRAM will be popular in 2002 and 2 Gb/s/pin in 2004 for high-end graphics applications. Random-access times in the range of 5 ns for SRAM and 20 ns for DRAM range and 1 Gb/s/pin DRAM will be available in 2002, and even faster (frequency, latency) memories will be required for high-end network systems such as OC-768-based switches and routers and beyond. Mobile platforms, especially 3 G phones and PDAs, are driving low-voltage low-power memories. Standby power of DRAM and pseudo-SRAM has been reduced drastically over the last 2 years. 1.8 V DRAM will be in volume production in 2002 and 1.0 V DRAM is expected in 2005 for longer battery life and moving-picture capability of mobile applications. The small-form-factor requirement of mobile phones and consumer applications such as PDA, and DSC will expedite various multi-chip-package solutions such as SRAM+Flash, DRAM+Flash, and SRAM+DRAM+Flash. Recent digital convergence and the rapid reduction of

Advanced integrated-circuit reliability simulation including dynamic stress effects

/MB of mass storage flash memory increased the usage of flash memory in various mobile and consumer applications. Semiconductor memory will continue to follow Moores Law for at least the next 10 years and will be lead by mass storage flash memory technology. Memory requirement of various IT platforms will continue to increase the trend of MB/system and MB/person.

A highly practical modified LOCOS isolation technology for the 256 Mbit DRAM

A systematic approach to predict semiconductor degradation effects using reliability simulation is described. The DC degradation monitor is first extracted during transient circuit simulation. An AC degradation factor is then used to determine circuit performance degradation. By using these techniques on the design of CMOS components, proper long-term reliability can be achieved for high-speed circuits. Experimental results on digital circuits using an industrial submicrometer technology demonstrate the effectiveness of this approach in reliable VLSI circuit design. Results on two-input NAND gates, DRAM precharging circuit, and SRAM control circuits are presented. >

A 0.15 /spl mu/m NAND flash technology with 0.11 /spl mu/m/sup 2/ cell size for 1 Gbit flash memory

We have developed a modified LOCOS isolation technology for the 256 Mbit DRAM. This novel Poly-Si Spacer LOCOS (PSL) isolation has been applied to build a 16 Mbit density DRAM with 256 Mbit (0.3 /spl mu/m) design rules. With the PSL isolation process, low birds beak encroachment, good vertical profile, clear definition of the active and field boundaries, high punchthrough voltage, and low leakage current have been achieved by simple fabrication processes.<<ETX>>

Advanced integration technology for a highly scalable SOI DRAM with SOC (Silicon-On-Capacitors)

A new 1 Gb NAND flash technology with high-aspect-ratio floating gate, tungsten bit line and poly-Si source line has been developed. It is fabricated using 0.15 /spl mu/m photolithography, shallow trench isolation (STI), highly selective gate etching, damascene and chemical-mechanical polishing (CMP) processes. Since thick poly-Si is deposited and its sidewall has an inclined profile by anisotropic etching, narrow floating gate space (/spl sim/80 nm) under the design rule and a high coupling ratio (/spl sim/0.75) are obtained. To interconnect the NAND cell array, the poly-Si source is connected to every string as a common line and the tungsten bit line is damascened over the entire string. These double-layer interconnections lead to simple process and reduced steps. Thus, for the first time, a prototype 1 Gb NAND flash memory with an extremely small cell size of 0.11 /spl mu/m/sup 2/ has been achieved.

Semiconductor memories for IT

A fully planarized 16 Mb SOI DRAM has been successfully fabricated featuring pattern-bonded SOI (PBSOI), CMP processes, STI (Shallow Trench Isolation) and the silicon-on-capacitor (SOC) structure with 0.3 um technology using i-line lithography. The floating body effects of cell and peripheral SOI transistors are suppressed by the LIF (Local Implantation post Field oxidation) and halo implantation. The fully planarized process with SOC structure is established for multi-gigabit DRAM and embedded memory devices.

Integrated-circuit reliability simulation including dynamic stress effects

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