S.T. Ahn

Highly Reliable 256Mb PRAM with Advanced Ring Contact Technology and Novel Encapsulating Technology

Advanced ring type technology and encapsulating scheme were developed to fabricate highly manufacturable and reliable 256Mb PRAM. Very uniform BEC area was prepared by the advanced ring type technology in which core dielectrics were optimized for cell contact CMP process. In addition, relatively high set resistance was stabilized from encapsulating Ge2Sb2Te5 (GST) stack with blocking layers, thus giving rise to a wide sensing window. These advanced ring type and encapsulating technologies can provide great potentials of developing high density 512Mb PRAM and beyond

Highly manufacturable process technology for reliable 256 Mbit and 1 Gbit DRAMs

Ta/sub 2/O/sub 5/ dielectric on poly-Si cylinder capacitors, chemical-mechanical polishing (CMP) planarization, pure W bit-line, and Al reflow were integrated into a highly manufacturable DRAM process technology. This technology provided larger process margin, higher reliability, and better design flexibility. In addition, the critical steps of the new process has been reduced by 25% of those of the conventional process. The manufacturability of the technology has been proven by applying it to 16 Mbit density DRAMs with 256 Mbit design rule (0.28 /spl mu/m).<<ETX>>

A novel booster plate technology in high density NAND flash memories for voltage scaling-down and zero program disturbance

The booster plate in NAND flash memory cells gives numerous advantages: the reduction of program, erase and pass voltages, zero program disturbance and increased cell current. At the same time, it is simple to integrate the technology to the conventional fabrication processes. It is expected that the booster plate technology will become one of the key technologies for achieving high density memories such as 256 Mbit and 1 Gbit NAND flash.

Scaling down of tunnel oxynitride in NAND flash memory: oxynitride selection and reliabilities

The selection of a manufacturable furnace-grown oxynitride process and reliability issues of the scaled tunnel oxide are examined. As the oxide thickness is scaled down, the cycling endurance, read life time and program disturb characteristics in a NAND flash memory with the tunnel oxynitride are improved compared to the conventional dry oxide.

A triple polysilicon stacked flash memory cell with wordline self-boosting programming

A novel triple polysilicon stacked flash cell by the wordline boosting is proposed as a solution for a low voltage operation. The third gate named as booster gate is simply stacked and self-aligned on the conventional control gate. The successively coupled booster gate bias in addition to the precharged control gate voltage is a key to increase the floating gate potential. A new NAND flash cell array with 0.51 /spl mu//sup 2/ cell size is fabricated using the 0.32 /spl mu/m process technology. A triple stacked polysilicon structure is patterned with a single self-alignment etching technology. With the booster gate bias, significantly enhanced coupling to the floating gate is obtained through the self-boosted control gate voltage. Thus, for the first time, a 11 V programming voltage is achieved at 300 /spl mu/s programming time in the multi-bit NAND flash cell.

A novel Al-reflow process using surface modification by the ECR plasma treatment and its application to the 256 Mbit DRAM

A novel Al-reflow process with the electron cyclotron resonance (ECR) plasma treatment for the modification of underlayers was developed in a vacuum isolated sputtering equipment. The key feature of this technology is the introduction of the in-situ ECR plasma treatment for the modification of the surface characteristics such as surface morphology and stoichiometry of the TiN wetting/barrier layer. High wettability of the Al film was obtained on the ECR-treated TiN surface, producing a conformal Al film on the sidewall of the contact hole before the reflow process. Consequently, complete filling of contact holes with Al was achieved in deep sub-micron contact holes with a high aspect ratio. This study has demonstrated that the Al-reflow process can be extended to the process of the devices of 256 Mbit DRAM generation and beyond.<<ETX>>

A highly practical modified LOCOS isolation technology for the 256 Mbit DRAM

We have developed a modified LOCOS isolation technology for the 256 Mbit DRAM. This novel Poly-Si Spacer LOCOS (PSL) isolation has been applied to build a 16 Mbit density DRAM with 256 Mbit (0.3 /spl mu/m) design rules. With the PSL isolation process, low birds beak encroachment, good vertical profile, clear definition of the active and field boundaries, high punchthrough voltage, and low leakage current have been achieved by simple fabrication processes.<<ETX>>

Self-Aligned LOCOS/Trench (SALOT) combination isolation technology planarized by chemical mechanical polishing

A novel isolation technology of Self-Aligned LOCOS/Trench (SALOT) has been developed for the isolation of deep-sub micron devices. SALOT has the isolation structure of a Poly-Buffered LOCOS (PBL) field oxide and a self-aligned trench at the center of a narrow field region planarized by the Chemical Mechanical Polishing (CMP) process. With SALOT, dishing was effectively suppressed for field regions as wide as 4 mm. Devices with SALOT show excellent isolation characteristics and gate oxide quality, and low leakage currents. SALOT can be scaled down to the 1 Gbit DRAM generation.<<ETX>>

Ta/sub 2/O/sub 5/ capacitors for 1 Gbit DRAM and beyond

A thermally robust Ta/sub 2/O/sub 5/ capacitor applicable to the 1 Gbit DRAM and beyond was developed. From the degradation-free Ta/sub 2/O/sub 5/ capacitor with a TiN/poly-Si top electrode, the sputtered-TiN was replaced by the PECVD-WN to improve the step coverage for the complicated capacitor structure. The Ta/sub 2/O/sub 5/ capacitor with a PECVD-WN/poly-Si top electrode had a better thermal stability in the complicated capacitor structure than that with sputtered-TiN/poly-Si, as a result. Capacitance of more than 90 fF/cell and leakage current lower than 2/spl times/10/sup -15/ A/cell were obtained by applying the WN/poly-Si top electrode and a 3.5 nm Ta/sub 2/O/sub 5/ capacitor dielectric to a cylindrical capacitor with rugged poly-Si surface (projection area=0.4 /spl mu/m/sup 2/). TDDB measurement predicted longer lifetime than 10 years at the device operating voltage. This new capacitor structure, therefore, surpasses the requirements for the 1 Gbit DRAM.<<ETX>>

Process integration for the high speed NAND flash memory cell

The high speed NAND flash memory cell with a read access time of 80 ns has been demonstrated. In the process integration of the high speed cell, complementary polycide bit lines with the ground selection scheme, self-aligned field through implantation, and metal source line have been introduced. The reliable high speed NAND cell operation has been achieved by enhanced sensing voltage swing, increased cell current and reduced bit line loading.